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drm/amdgpu: enable ABGR and XBGR formats (v2)

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Add support for DRM_FORMAT_{A,X}BGR8888 in amdgpu with amd dc disabled

(v2) Crossbar registers are defined and used to swap red and blue channels,
     keeping the existing coding style in each of the dce modules.
     After setting crossbar bits in fb_swap, use bitwise OR for big endian
     where required in DCE6 and DCE8 which do not rely on REG_SET_FIELD()

Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Mauro Rossi
2018-08-12 21:43:02 +02:00
committed by Alex Deucher
parent bcd47f60ab
commit 00ecc6e6d4
6 changed files with 82 additions and 0 deletions
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20
drivers/gpu/drm/amd/amdgpu/si_enums.h
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@@ -46,6 +46,26 @@
#define GRPH_ENDIAN_8IN16 1
#define GRPH_ENDIAN_8IN32 2
#define GRPH_ENDIAN_8IN64 3
#define GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)
#define GRPH_RED_SEL_R 0
#define GRPH_RED_SEL_G 1
#define GRPH_RED_SEL_B 2
#define GRPH_RED_SEL_A 3
#define GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)
#define GRPH_GREEN_SEL_G 0
#define GRPH_GREEN_SEL_B 1
#define GRPH_GREEN_SEL_A 2
#define GRPH_GREEN_SEL_R 3
#define GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8)
#define GRPH_BLUE_SEL_B 0
#define GRPH_BLUE_SEL_A 1
#define GRPH_BLUE_SEL_R 2
#define GRPH_BLUE_SEL_G 3
#define GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10)
#define GRPH_ALPHA_SEL_A 0
#define GRPH_ALPHA_SEL_R 1
#define GRPH_ALPHA_SEL_G 2
#define GRPH_ALPHA_SEL_B 3
#define GRPH_DEPTH(x) (((x) & 0x3) << 0)
#define GRPH_DEPTH_8BPP 0