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drm/amd/display: Implement PCON regulated autonomous mode handling
[Why/How] DP spec has been updated recently to make regulated autonomous mode more well-defined. In case any PCON vendors choose to implement regulated autonomous mode in the future, pre-emptively add handling for the regulated autonomous mode based on current spec. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
committed by
Alex Deucher
parent
8a21da2842
commit
084e073544
@@ -265,6 +265,8 @@ static uint32_t intersect_frl_link_bw_support(
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supported_bw_in_kbps = 18000000;
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else if (hdmi_encoded_link_bw.bits.BW_9Gbps)
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supported_bw_in_kbps = 9000000;
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else if (hdmi_encoded_link_bw.bits.FRL_LINK_TRAINING_FINISHED)
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supported_bw_in_kbps = 0; /* This case should only get hit in regulated autonomous mode. */
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return supported_bw_in_kbps;
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}
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@@ -1075,6 +1077,48 @@ static enum dc_status wake_up_aux_channel(struct dc_link *link)
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return DC_OK;
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}
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static void read_and_intersect_post_frl_lt_status(
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struct dc_link *link)
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{
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union autonomous_mode_and_frl_link_status autonomous_mode_caps = {0};
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union hdmi_tx_link_status hdmi_tx_link_status = {0};
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union hdmi_encoded_link_bw hdmi_encoded_link_bw = {0};
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/* Check if dongle supports regulated autonomous mode. */
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core_link_read_dpcd(link, DP_REGULATED_AUTONOMOUS_MODE_SUPPORTED_AND_HDMI_LINK_TRAINING_STATUS,
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&autonomous_mode_caps.raw, sizeof(autonomous_mode_caps));
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link->dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support =
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autonomous_mode_caps.bits.REGULATED_AUTONOMOUS_MODE_SUPPORTED;
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if (link->dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support) {
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DC_LOG_DC("%s: PCON supports regulated autonomous mode.\n", __func__);
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core_link_read_dpcd(link, DP_PCON_HDMI_TX_LINK_STATUS,
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&hdmi_tx_link_status.raw, sizeof(hdmi_tx_link_status));
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}
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// Intersect reported max link bw support with the supported link rate post FRL link training
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if (core_link_read_dpcd(link, DP_PCON_HDMI_POST_FRL_STATUS,
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&hdmi_encoded_link_bw.raw, sizeof(hdmi_encoded_link_bw)) == DC_OK) {
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if (link->dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support &&
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(!hdmi_tx_link_status.bits.HDMI_TX_READY_STATUS ||
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!hdmi_encoded_link_bw.bits.FRL_LINK_TRAINING_FINISHED)) {
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DC_LOG_WARNING("%s: PCON TX link training has not finished.\n", __func__);
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/* Link training not finished, ignore values from this DPCD reg. */
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return;
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}
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link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = intersect_frl_link_bw_support(
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link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps,
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hdmi_encoded_link_bw);
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DC_LOG_DC("%s: pcon frl link bw = %u\n", __func__,
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link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps);
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}
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}
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static void get_active_converter_info(
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uint8_t data, struct dc_link *link)
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{
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@@ -1163,21 +1207,12 @@ static void get_active_converter_info(
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hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
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if (link->dc->caps.dp_hdmi21_pcon_support) {
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union hdmi_encoded_link_bw hdmi_encoded_link_bw;
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link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps =
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link_bw_kbps_from_raw_frl_link_rate_data(
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hdmi_color_caps.bits.MAX_ENCODED_LINK_BW_SUPPORT);
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// Intersect reported max link bw support with the supported link rate post FRL link training
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if (core_link_read_dpcd(link, DP_PCON_HDMI_POST_FRL_STATUS,
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&hdmi_encoded_link_bw.raw, sizeof(hdmi_encoded_link_bw)) == DC_OK) {
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link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = intersect_frl_link_bw_support(
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link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps,
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hdmi_encoded_link_bw);
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DC_LOG_DC("%s: pcon frl link bw = %u\n", __func__,
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link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps);
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}
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read_and_intersect_post_frl_lt_status(link);
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if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0)
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link->dpcd_caps.dongle_caps.extendedCapValid = true;
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