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drm/xe/vm: Use for_each_tlb_inval() to calculate invalidation fences

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ops_execute() calculates the size of a fence array based on
XE_MAX_GT_PER_TILE, while the code that actually fills in the fence
array uses a for_each_tlb_inval() iterator.  This works out okay today
since both approaches come up with the same number of invalidation
fences (2: primary GT invalidation + media GT invalidation), but could
be problematic in the future if there isn't a 1:1 relationship between
TLBs needing invalidation and potential GTs on the tile.

Adjust the allocation code to use the same for_each_tlb_inval()
counting logic as the code that fills the array to future-proof the
code.

Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20251118202604.3715782-2-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
This commit is contained in:
Matt Roper
2025-11-18 12:26:05 -08:00
parent fa18290bf0
commit 0a4c2ddc71
1 changed files with 7 additions and 8 deletions
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15
drivers/gpu/drm/xe/xe_vm.c
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@@ -3104,19 +3104,19 @@ static struct dma_fence *ops_execute(struct xe_vm *vm,
struct dma_fence *fence = NULL;
struct dma_fence **fences = NULL;
struct dma_fence_array *cf = NULL;
int number_tiles = 0, current_fence = 0, n_fence = 0, err;
int number_tiles = 0, current_fence = 0, n_fence = 0, err, i;
u8 id;
number_tiles = vm_ops_setup_tile_args(vm, vops);
if (number_tiles == 0)
return ERR_PTR(-ENODATA);
if (vops->flags & XE_VMA_OPS_FLAG_SKIP_TLB_WAIT) {
for_each_tile(tile, vm->xe, id)
++n_fence;
} else {
for_each_tile(tile, vm->xe, id)
n_fence += (1 + XE_MAX_GT_PER_TILE);
for_each_tile(tile, vm->xe, id) {
++n_fence;
if (!(vops->flags & XE_VMA_OPS_FLAG_SKIP_TLB_WAIT))
for_each_tlb_inval(i)
++n_fence;
}
fences = kmalloc_array(n_fence, sizeof(*fences), GFP_KERNEL);
@@ -3146,7 +3146,6 @@ static struct dma_fence *ops_execute(struct xe_vm *vm,
for_each_tile(tile, vm->xe, id) {
struct xe_exec_queue *q = vops->pt_update_ops[tile->id].q;
int i;
fence = NULL;
if (!vops->pt_update_ops[id].num_ops)