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drm/amdgpu: refine MES register print for devices of hive

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[Why]
Register access print missed device info.

[How]
Using dev_xxx instead of DRM_xxx to indicate which device
of a hive is the message for.

Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yifan Zha
2025-04-21 17:06:52 +08:00
committed by Alex Deucher
parent 3805e6959c
commit 161949dd71
1 changed files with 9 additions and 9 deletions
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18
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
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@@ -428,7 +428,7 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg)
uint32_t *read_val_ptr;
if (amdgpu_device_wb_get(adev, &addr_offset)) {
DRM_ERROR("critical bug! too many mes readers\n");
dev_err(adev->dev, "critical bug! too many mes readers\n");
goto error;
}
read_val_gpu_addr = adev->wb.gpu_addr + (addr_offset * 4);
@@ -438,13 +438,13 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg)
op_input.read_reg.buffer_addr = read_val_gpu_addr;
if (!adev->mes.funcs->misc_op) {
DRM_ERROR("mes rreg is not supported!\n");
dev_err(adev->dev, "mes rreg is not supported!\n");
goto error;
}
r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
if (r)
DRM_ERROR("failed to read reg (0x%x)\n", reg);
dev_err(adev->dev, "failed to read reg (0x%x)\n", reg);
else
val = *(read_val_ptr);
@@ -465,14 +465,14 @@ int amdgpu_mes_wreg(struct amdgpu_device *adev,
op_input.write_reg.reg_value = val;
if (!adev->mes.funcs->misc_op) {
DRM_ERROR("mes wreg is not supported!\n");
dev_err(adev->dev, "mes wreg is not supported!\n");
r = -EINVAL;
goto error;
}
r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
if (r)
DRM_ERROR("failed to write reg (0x%x)\n", reg);
dev_err(adev->dev, "failed to write reg (0x%x)\n", reg);
error:
return r;
@@ -492,14 +492,14 @@ int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
op_input.wrm_reg.mask = mask;
if (!adev->mes.funcs->misc_op) {
DRM_ERROR("mes reg_write_reg_wait is not supported!\n");
dev_err(adev->dev, "mes reg_write_reg_wait is not supported!\n");
r = -EINVAL;
goto error;
}
r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
if (r)
DRM_ERROR("failed to reg_write_reg_wait\n");
dev_err(adev->dev, "failed to reg_write_reg_wait\n");
error:
return r;
@@ -517,14 +517,14 @@ int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,
op_input.wrm_reg.mask = mask;
if (!adev->mes.funcs->misc_op) {
DRM_ERROR("mes reg wait is not supported!\n");
dev_err(adev->dev, "mes reg wait is not supported!\n");
r = -EINVAL;
goto error;
}
r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
if (r)
DRM_ERROR("failed to reg_write_reg_wait\n");
dev_err(adev->dev, "failed to reg_write_reg_wait\n");
error:
return r;