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drm/amd/display: refactor dcn10 hw_sequencer to new reg access style

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Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin
2017-07-05 06:57:49 -04:00
committed by Alex Deucher
parent fa6ecfc67a
commit 184debdbd8
3 changed files with 342 additions and 429 deletions
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177
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
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@@ -122,11 +122,56 @@
HWSEQ_PHYPLL_REG_LIST(CRTC)
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#define HWSEQ_DCN1_REG_LIST()\
#define HWSEQ_DCN_REG_LIST()\
HWSEQ_PIXEL_RATE_REG_LIST(OTG), \
HWSEQ_PHYPLL_REG_LIST(OTG)
HWSEQ_PHYPLL_REG_LIST(OTG), \
SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 0), \
SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 1), \
SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 2), \
SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 3), \
SRII(DCHUBP_CNTL, HUBP, 0), \
SRII(DCHUBP_CNTL, HUBP, 1), \
SRII(DCHUBP_CNTL, HUBP, 2), \
SRII(DCHUBP_CNTL, HUBP, 3), \
SRII(HUBP_CLK_CNTL, HUBP, 0), \
SRII(HUBP_CLK_CNTL, HUBP, 1), \
SRII(HUBP_CLK_CNTL, HUBP, 2), \
SRII(HUBP_CLK_CNTL, HUBP, 3), \
SRII(DPP_CONTROL, DPP_TOP, 0), \
SRII(DPP_CONTROL, DPP_TOP, 1), \
SRII(DPP_CONTROL, DPP_TOP, 2), \
SRII(DPP_CONTROL, DPP_TOP, 3), \
SR(REFCLK_CNTL), \
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
SR(DC_IP_REQUEST_CNTL), \
SR(DOMAIN0_PG_CONFIG), \
SR(DOMAIN1_PG_CONFIG), \
SR(DOMAIN2_PG_CONFIG), \
SR(DOMAIN3_PG_CONFIG), \
SR(DOMAIN4_PG_CONFIG), \
SR(DOMAIN5_PG_CONFIG), \
SR(DOMAIN6_PG_CONFIG), \
SR(DOMAIN7_PG_CONFIG), \
SR(DOMAIN0_PG_STATUS), \
SR(DOMAIN1_PG_STATUS), \
SR(DOMAIN2_PG_STATUS), \
SR(DOMAIN3_PG_STATUS), \
SR(DOMAIN4_PG_STATUS), \
SR(DOMAIN5_PG_STATUS), \
SR(DOMAIN6_PG_STATUS), \
SR(DOMAIN7_PG_STATUS), \
SR(DIO_MEM_PWR_CTRL), \
SR(DCCG_GATE_DISABLE_CNTL), \
SR(DCCG_GATE_DISABLE_CNTL2), \
SR(DCFCLK_CNTL)
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#define HWSEQ_DCN1_REG_LIST()\
HWSEQ_DCN_REG_LIST()
#endif
struct dce_hwseq_registers {
uint32_t DCFE_CLOCK_CONTROL[6];
uint32_t DCFEV_CLOCK_CONTROL;
@@ -134,13 +179,39 @@ struct dce_hwseq_registers {
uint32_t BLND_V_UPDATE_LOCK[6];
uint32_t BLND_CONTROL[6];
uint32_t BLNDV_CONTROL;
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
/* DCE + DCN */
#endif
uint32_t CRTC_H_BLANK_START_END[6];
uint32_t PIXEL_RATE_CNTL[6];
uint32_t PHYPLL_PIXEL_RATE_CNTL[6];
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
uint32_t OTG_GLOBAL_SYNC_STATUS[4];
uint32_t DCHUBP_CNTL[4];
uint32_t HUBP_CLK_CNTL[4];
uint32_t DPP_CONTROL[4];
uint32_t REFCLK_CNTL;
uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;
uint32_t DC_IP_REQUEST_CNTL;
uint32_t DOMAIN0_PG_CONFIG;
uint32_t DOMAIN1_PG_CONFIG;
uint32_t DOMAIN2_PG_CONFIG;
uint32_t DOMAIN3_PG_CONFIG;
uint32_t DOMAIN4_PG_CONFIG;
uint32_t DOMAIN5_PG_CONFIG;
uint32_t DOMAIN6_PG_CONFIG;
uint32_t DOMAIN7_PG_CONFIG;
uint32_t DOMAIN0_PG_STATUS;
uint32_t DOMAIN1_PG_STATUS;
uint32_t DOMAIN2_PG_STATUS;
uint32_t DOMAIN3_PG_STATUS;
uint32_t DOMAIN4_PG_STATUS;
uint32_t DOMAIN5_PG_STATUS;
uint32_t DOMAIN6_PG_STATUS;
uint32_t DOMAIN7_PG_STATUS;
uint32_t DIO_MEM_PWR_CTRL;
uint32_t DCCG_GATE_DISABLE_CNTL;
uint32_t DCCG_GATE_DISABLE_CNTL2;
uint32_t DCFCLK_CNTL;
#endif
};
/* set field name */
#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
@@ -202,12 +273,52 @@ struct dce_hwseq_registers {
HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\
#define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, OTG0_)
HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, OTG0_),\
HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR, mask_sh), \
HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_OCCURRED, mask_sh), \
HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh), \
HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh), \
HWS_SF(HUBP0_, HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh), \
HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh)
#endif
#define HWSEQ_REG_FIED_LIST(type) \
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\
HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \
HWS_SF(DPP_TOP0_, DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh)
#endif
#define HWSEQ_REG_FIELD_LIST(type) \
type DCFE_CLOCK_ENABLE; \
type DCFEV_CLOCK_ENABLE; \
type DC_MEM_GLOBAL_PWR_REQ_DIS; \
@@ -225,12 +336,56 @@ struct dce_hwseq_registers {
type PHYPLL_PIXEL_RATE_SOURCE; \
type PIXEL_RATE_PLL_SOURCE; \
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#define HWSEQ_DCN_REG_FIELD_LIST(type) \
type VUPDATE_NO_LOCK_EVENT_CLEAR; \
type VUPDATE_NO_LOCK_EVENT_OCCURRED; \
type HUBP_NO_OUTSTANDING_REQ; \
type HUBP_VTG_SEL; \
type HUBP_CLOCK_ENABLE; \
type DPP_CLOCK_ENABLE; \
type DPPCLK_RATE_CONTROL; \
type DCHUBBUB_GLOBAL_TIMER_ENABLE; \
type IP_REQUEST_EN; \
type DOMAIN0_POWER_FORCEON; \
type DOMAIN0_POWER_GATE; \
type DOMAIN1_POWER_FORCEON; \
type DOMAIN1_POWER_GATE; \
type DOMAIN2_POWER_FORCEON; \
type DOMAIN2_POWER_GATE; \
type DOMAIN3_POWER_FORCEON; \
type DOMAIN3_POWER_GATE; \
type DOMAIN4_POWER_FORCEON; \
type DOMAIN4_POWER_GATE; \
type DOMAIN5_POWER_FORCEON; \
type DOMAIN5_POWER_GATE; \
type DOMAIN6_POWER_FORCEON; \
type DOMAIN6_POWER_GATE; \
type DOMAIN7_POWER_FORCEON; \
type DOMAIN7_POWER_GATE; \
type DOMAIN0_PGFSM_PWR_STATUS; \
type DOMAIN1_PGFSM_PWR_STATUS; \
type DOMAIN2_PGFSM_PWR_STATUS; \
type DOMAIN3_PGFSM_PWR_STATUS; \
type DOMAIN4_PGFSM_PWR_STATUS; \
type DOMAIN5_PGFSM_PWR_STATUS; \
type DOMAIN6_PGFSM_PWR_STATUS; \
type DOMAIN7_PGFSM_PWR_STATUS; \
type DCFCLK_GATE_DIS;
#endif
struct dce_hwseq_shift {
HWSEQ_REG_FIED_LIST(uint8_t)
HWSEQ_REG_FIELD_LIST(uint8_t)
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
HWSEQ_DCN_REG_FIELD_LIST(uint8_t)
#endif
};
struct dce_hwseq_mask {
HWSEQ_REG_FIED_LIST(uint32_t)
HWSEQ_REG_FIELD_LIST(uint32_t)
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
HWSEQ_DCN_REG_FIELD_LIST(uint32_t)
#endif
};