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Merge tag 'amd-drm-next-6.16-2025-05-09' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-6.16-2025-05-09: amdgpu: - IPS fixes - DSC cleanup - DC Scaling updates - DC FP fixes - Fused I2C-over-AUX updates - SubVP fixes - Freesync fix - DMUB AUX fixes - VCN fix - Hibernation fixes - HDP fixes - DCN 2.1 fixes - DPIA fixes - DMUB updates - Use drm_file_err in amdgpu - Enforce isolation updates - Use new dma_fence helpers - USERQ fixes - Documentation updates - Misc code cleanups - SR-IOV updates - RAS updates - PSP 12 cleanups amdkfd: - Update error messages for SDMA - Userptr updates drm: - Add drm_file_err function dma-buf: - Add a helper to sort and deduplicate dma_fence arrays From: Alex Deucher <alexander.deucher@amd.com> Link: https://lore.kernel.org/r/20250509230951.3871914-1-alexander.deucher@amd.com Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
@@ -54,6 +54,9 @@ extern "C" {
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#define DRM_AMDGPU_VM 0x13
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#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
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#define DRM_AMDGPU_SCHED 0x15
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#define DRM_AMDGPU_USERQ 0x16
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#define DRM_AMDGPU_USERQ_SIGNAL 0x17
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#define DRM_AMDGPU_USERQ_WAIT 0x18
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#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
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#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
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@@ -71,6 +74,9 @@ extern "C" {
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#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
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#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
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#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
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#define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
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#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)
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#define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)
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/**
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* DOC: memory domains
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@@ -319,6 +325,260 @@ union drm_amdgpu_ctx {
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union drm_amdgpu_ctx_out out;
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};
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/* user queue IOCTL operations */
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#define AMDGPU_USERQ_OP_CREATE 1
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#define AMDGPU_USERQ_OP_FREE 2
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/* queue priority levels */
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/* low < normal low < normal high < high */
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#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK 0x3
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#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT 0
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#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW 0
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#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW 1
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#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH 2
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#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH 3 /* admin only */
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/* for queues that need access to protected content */
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#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE (1 << 2)
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/*
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* This structure is a container to pass input configuration
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* info for all supported userqueue related operations.
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* For operation AMDGPU_USERQ_OP_CREATE: user is expected
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* to set all fields, excep the parameter 'queue_id'.
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* For operation AMDGPU_USERQ_OP_FREE: the only input parameter expected
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* to be set is 'queue_id', eveything else is ignored.
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*/
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struct drm_amdgpu_userq_in {
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/** AMDGPU_USERQ_OP_* */
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__u32 op;
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/** Queue id passed for operation USERQ_OP_FREE */
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__u32 queue_id;
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/** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */
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__u32 ip_type;
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/**
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* @doorbell_handle: the handle of doorbell GEM object
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* associated with this userqueue client.
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*/
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__u32 doorbell_handle;
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/**
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* @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo.
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* Kernel will generate absolute doorbell offset using doorbell_handle
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* and doorbell_offset in the doorbell bo.
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*/
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__u32 doorbell_offset;
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/**
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* @flags: flags used for queue parameters
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*/
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__u32 flags;
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/**
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* @queue_va: Virtual address of the GPU memory which holds the queue
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* object. The queue holds the workload packets.
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*/
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__u64 queue_va;
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/**
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* @queue_size: Size of the queue in bytes, this needs to be 256-byte
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* aligned.
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*/
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__u64 queue_size;
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/**
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* @rptr_va : Virtual address of the GPU memory which holds the ring RPTR.
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* This object must be at least 8 byte in size and aligned to 8-byte offset.
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*/
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__u64 rptr_va;
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/**
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* @wptr_va : Virtual address of the GPU memory which holds the ring WPTR.
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* This object must be at least 8 byte in size and aligned to 8-byte offset.
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*
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* Queue, RPTR and WPTR can come from the same object, as long as the size
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* and alignment related requirements are met.
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*/
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__u64 wptr_va;
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/**
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* @mqd: MQD (memory queue descriptor) is a set of parameters which allow
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* the GPU to uniquely define and identify a usermode queue.
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*
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* MQD data can be of different size for different GPU IP/engine and
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* their respective versions/revisions, so this points to a __u64 *
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* which holds IP specific MQD of this usermode queue.
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*/
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__u64 mqd;
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/**
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* @size: size of MQD data in bytes, it must match the MQD structure
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* size of the respective engine/revision defined in UAPI for ex, for
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* gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11).
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*/
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__u64 mqd_size;
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};
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/* The structure to carry output of userqueue ops */
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struct drm_amdgpu_userq_out {
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/**
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* For operation AMDGPU_USERQ_OP_CREATE: This field contains a unique
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* queue ID to represent the newly created userqueue in the system, otherwise
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* it should be ignored.
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*/
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__u32 queue_id;
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__u32 _pad;
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};
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union drm_amdgpu_userq {
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struct drm_amdgpu_userq_in in;
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struct drm_amdgpu_userq_out out;
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};
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/* GFX V11 IP specific MQD parameters */
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struct drm_amdgpu_userq_mqd_gfx11 {
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/**
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* @shadow_va: Virtual address of the GPU memory to hold the shadow buffer.
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* Use AMDGPU_INFO_IOCTL to find the exact size of the object.
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*/
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__u64 shadow_va;
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/**
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* @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
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* Use AMDGPU_INFO_IOCTL to find the exact size of the object.
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*/
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__u64 csa_va;
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};
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/* GFX V11 SDMA IP specific MQD parameters */
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struct drm_amdgpu_userq_mqd_sdma_gfx11 {
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/**
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* @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
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* This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL
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* to get the size.
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*/
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__u64 csa_va;
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};
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/* GFX V11 Compute IP specific MQD parameters */
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struct drm_amdgpu_userq_mqd_compute_gfx11 {
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/**
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* @eop_va: Virtual address of the GPU memory to hold the EOP buffer.
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* This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL
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* to get the size.
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*/
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__u64 eop_va;
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};
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/* userq signal/wait ioctl */
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struct drm_amdgpu_userq_signal {
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/**
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* @queue_id: Queue handle used by the userq fence creation function
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* to retrieve the WPTR.
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*/
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__u32 queue_id;
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__u32 pad;
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/**
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* @syncobj_handles: The list of syncobj handles submitted by the user queue
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* job to be signaled.
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*/
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__u64 syncobj_handles;
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/**
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* @num_syncobj_handles: A count that represents the number of syncobj handles in
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* @syncobj_handles.
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*/
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__u64 num_syncobj_handles;
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/**
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* @bo_read_handles: The list of BO handles that the submitted user queue job
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* is using for read only. This will update BO fences in the kernel.
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*/
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__u64 bo_read_handles;
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/**
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* @bo_write_handles: The list of BO handles that the submitted user queue job
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* is using for write only. This will update BO fences in the kernel.
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*/
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__u64 bo_write_handles;
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/**
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* @num_bo_read_handles: A count that represents the number of read BO handles in
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* @bo_read_handles.
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*/
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__u32 num_bo_read_handles;
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/**
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* @num_bo_write_handles: A count that represents the number of write BO handles in
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* @bo_write_handles.
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*/
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__u32 num_bo_write_handles;
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};
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struct drm_amdgpu_userq_fence_info {
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/**
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* @va: A gpu address allocated for each queue which stores the
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* read pointer (RPTR) value.
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*/
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__u64 va;
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/**
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* @value: A 64 bit value represents the write pointer (WPTR) of the
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* queue commands which compared with the RPTR value to signal the
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* fences.
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*/
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__u64 value;
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};
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struct drm_amdgpu_userq_wait {
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/**
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* @waitq_id: Queue handle used by the userq wait IOCTL to retrieve the
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* wait queue and maintain the fence driver references in it.
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*/
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__u32 waitq_id;
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__u32 pad;
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/**
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* @syncobj_handles: The list of syncobj handles submitted by the user queue
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* job to get the va/value pairs.
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*/
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__u64 syncobj_handles;
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/**
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* @syncobj_timeline_handles: The list of timeline syncobj handles submitted by
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* the user queue job to get the va/value pairs at given @syncobj_timeline_points.
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*/
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__u64 syncobj_timeline_handles;
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/**
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* @syncobj_timeline_points: The list of timeline syncobj points submitted by the
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* user queue job for the corresponding @syncobj_timeline_handles.
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*/
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__u64 syncobj_timeline_points;
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/**
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* @bo_read_handles: The list of read BO handles submitted by the user queue
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* job to get the va/value pairs.
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*/
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__u64 bo_read_handles;
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/**
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* @bo_write_handles: The list of write BO handles submitted by the user queue
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* job to get the va/value pairs.
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*/
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__u64 bo_write_handles;
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/**
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* @num_syncobj_timeline_handles: A count that represents the number of timeline
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* syncobj handles in @syncobj_timeline_handles.
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*/
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__u16 num_syncobj_timeline_handles;
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/**
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* @num_fences: This field can be used both as input and output. As input it defines
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* the maximum number of fences that can be returned and as output it will specify
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* how many fences were actually returned from the ioctl.
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*/
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__u16 num_fences;
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/**
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* @num_syncobj_handles: A count that represents the number of syncobj handles in
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* @syncobj_handles.
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*/
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__u32 num_syncobj_handles;
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/**
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* @num_bo_read_handles: A count that represents the number of read BO handles in
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* @bo_read_handles.
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*/
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__u32 num_bo_read_handles;
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/**
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* @num_bo_write_handles: A count that represents the number of write BO handles in
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* @bo_write_handles.
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*/
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__u32 num_bo_write_handles;
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/**
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* @out_fences: The field is a return value from the ioctl containing the list of
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* address/value pairs to wait for.
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*/
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__u64 out_fences;
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};
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/* vm ioctl */
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#define AMDGPU_VM_OP_RESERVE_VMID 1
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#define AMDGPU_VM_OP_UNRESERVE_VMID 2
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@@ -599,6 +859,19 @@ struct drm_amdgpu_gem_va {
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__u64 offset_in_bo;
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/** Specify mapping size. Must be correctly aligned. */
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__u64 map_size;
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/**
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* vm_timeline_point is a sequence number used to add new timeline point.
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*/
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__u64 vm_timeline_point;
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/**
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* The vm page table update fence is installed in given vm_timeline_syncobj_out
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* at vm_timeline_point.
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*/
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__u32 vm_timeline_syncobj_out;
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/** the number of syncobj handles in @input_fence_syncobj_handles */
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__u32 num_syncobj_handles;
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/** Array of sync object handle to wait for given input fences */
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__u64 input_fence_syncobj_handles;
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};
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#define AMDGPU_HW_IP_GFX 0
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@@ -940,6 +1213,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
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#define AMDGPU_INFO_MAX_IBS 0x22
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/* query last page fault info */
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#define AMDGPU_INFO_GPUVM_FAULT 0x23
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/* query FW object size and alignment */
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#define AMDGPU_INFO_UQ_FW_AREAS 0x24
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#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
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#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
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@@ -1198,6 +1473,9 @@ struct drm_amdgpu_info_device {
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__u32 csa_size;
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/* context save area base virtual alignment for gfx11 */
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__u32 csa_alignment;
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/* Userq IP mask (1 << AMDGPU_HW_IP_*) */
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__u32 userq_ip_mask;
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__u32 pad;
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};
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struct drm_amdgpu_info_hw_ip {
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@@ -1216,6 +1494,27 @@ struct drm_amdgpu_info_hw_ip {
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__u32 ip_discovery_version;
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};
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/* GFX metadata BO sizes and alignment info (in bytes) */
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struct drm_amdgpu_info_uq_fw_areas_gfx {
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/* shadow area size */
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__u32 shadow_size;
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/* shadow area base virtual mem alignment */
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__u32 shadow_alignment;
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/* context save area size */
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__u32 csa_size;
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/* context save area base virtual mem alignment */
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__u32 csa_alignment;
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};
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/* IP specific fw related information used in the
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* subquery AMDGPU_INFO_UQ_FW_AREAS
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*/
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struct drm_amdgpu_info_uq_fw_areas {
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union {
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struct drm_amdgpu_info_uq_fw_areas_gfx gfx;
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};
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};
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struct drm_amdgpu_info_num_handles {
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/** Max handles as supported by firmware for UVD */
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__u32 uvd_max_handles;
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@@ -1279,6 +1578,23 @@ struct drm_amdgpu_info_gpuvm_fault {
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__u32 vmhub;
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};
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struct drm_amdgpu_info_uq_metadata_gfx {
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/* shadow area size for gfx11 */
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__u32 shadow_size;
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/* shadow area base virtual alignment for gfx11 */
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__u32 shadow_alignment;
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/* context save area size for gfx11 */
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__u32 csa_size;
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/* context save area base virtual alignment for gfx11 */
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__u32 csa_alignment;
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};
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struct drm_amdgpu_info_uq_metadata {
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union {
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struct drm_amdgpu_info_uq_metadata_gfx gfx;
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};
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};
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/*
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* Supported GPU families
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*/
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@@ -536,6 +536,8 @@ enum kfd_smi_event {
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KFD_SMI_EVENT_QUEUE_EVICTION = 9,
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KFD_SMI_EVENT_QUEUE_RESTORE = 10,
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KFD_SMI_EVENT_UNMAP_FROM_GPU = 11,
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KFD_SMI_EVENT_PROCESS_START = 12,
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KFD_SMI_EVENT_PROCESS_END = 13,
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/*
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* max event number, as a flag bit to get events from all processes,
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@@ -651,6 +653,9 @@ struct kfd_ioctl_smi_events_args {
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"%lld -%d @%lx(%lx) %x %d\n", (ns), (pid), (addr), (size),\
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(node), (unmap_trigger)
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#define KFD_EVENT_FMT_PROCESS(pid, task_name)\
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"%x %s\n", (pid), (task_name)
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/**************************************************************************************************
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* CRIU IOCTLs (Checkpoint Restore In Userspace)
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*
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