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parisc: Don't enforce DMA completion order in cache flushes

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The only place we need to ensure all outstanding cache coherence
operations are complete is in invalidate_kernel_vmap_range. All
parisc drivers synchronize DMA operations internally and do not
call invalidate_kernel_vmap_range. We only need this for non-coherent
I/O operations.

Signed-off-by: John David Anglin <dave.anglin@bell.net>
Signed-off-by: Helge Deller <deller@gmx.de>
This commit is contained in:
John David Anglin
2022-03-30 14:42:30 +00:00
committed by Helge Deller
parent 41dc0b53bc
commit 1fc7db2401
3 changed files with 4 additions and 3 deletions
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3
arch/parisc/kernel/cache.c
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@@ -754,6 +754,9 @@ void invalidate_kernel_vmap_range(void *vaddr, int size)
unsigned long start = (unsigned long)vaddr;
unsigned long end = start + size;
/* Ensure DMA is complete */
asm_syncdma();
if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
(unsigned long)size >= parisc_cache_flush_threshold) {
flush_tlb_kernel_range(start, end);