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crypto: hisilicon - support querying the capability register

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Query the capability register status of accelerator devices
(SEC, HPRE and ZIP) through the debugfs interface, for example:
cat cap_regs. The purpose is to improve the robustness and
locability of hardware devices and drivers.

Signed-off-by: Qi Tao <taoqi10@huawei.com>
Signed-off-by: Chenghai Huang <huangchenghai2@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Qi Tao
2024-10-26 17:46:51 +08:00
committed by Herbert Xu
parent acb0ed8432
commit 2a69297eed
12 changed files with 396 additions and 111 deletions
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71
drivers/crypto/hisilicon/sec2/sec_main.c
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@@ -14,9 +14,9 @@
#include <linux/seq_file.h>
#include <linux/topology.h>
#include <linux/uacce.h>
#include "sec.h"
#define CAP_FILE_PERMISSION 0444
#define SEC_VF_NUM 63
#define SEC_QUEUE_NUM_V1 4096
#define PCI_DEVICE_ID_HUAWEI_SEC_PF 0xa255
@@ -167,11 +167,34 @@ static const struct hisi_qm_cap_info sec_basic_info[] = {
{SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
};
static const u32 sec_pre_store_caps[] = {
SEC_DRV_ALG_BITMAP_LOW,
SEC_DRV_ALG_BITMAP_HIGH,
SEC_DEV_ALG_BITMAP_LOW,
SEC_DEV_ALG_BITMAP_HIGH,
static const struct hisi_qm_cap_query_info sec_cap_query_info[] = {
{QM_RAS_NFE_TYPE, "QM_RAS_NFE_TYPE ", 0x3124, 0x0, 0x1C77, 0x7C77},
{QM_RAS_NFE_RESET, "QM_RAS_NFE_RESET ", 0x3128, 0x0, 0xC77, 0x6C77},
{QM_RAS_CE_TYPE, "QM_RAS_CE_TYPE ", 0x312C, 0x0, 0x8, 0x8},
{SEC_RAS_NFE_TYPE, "SEC_RAS_NFE_TYPE ", 0x3130, 0x0, 0x177, 0x60177},
{SEC_RAS_NFE_RESET, "SEC_RAS_NFE_RESET ", 0x3134, 0x0, 0x177, 0x177},
{SEC_RAS_CE_TYPE, "SEC_RAS_CE_TYPE ", 0x3138, 0x0, 0x88, 0xC088},
{SEC_CORE_INFO, "SEC_CORE_INFO ", 0x313c, 0x110404, 0x110404, 0x110404},
{SEC_CORE_EN, "SEC_CORE_EN ", 0x3140, 0x17F, 0x17F, 0xF},
{SEC_DRV_ALG_BITMAP_LOW_TB, "SEC_DRV_ALG_BITMAP_LOW ",
0x3144, 0x18050CB, 0x18050CB, 0x18670CF},
{SEC_DRV_ALG_BITMAP_HIGH_TB, "SEC_DRV_ALG_BITMAP_HIGH ",
0x3148, 0x395C, 0x395C, 0x395C},
{SEC_ALG_BITMAP_LOW, "SEC_ALG_BITMAP_LOW ",
0x314c, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
{SEC_ALG_BITMAP_HIGH, "SEC_ALG_BITMAP_HIGH ", 0x3150, 0x3FFF, 0x3FFF, 0x3FFF},
{SEC_CORE1_BITMAP_LOW, "SEC_CORE1_BITMAP_LOW ",
0x3154, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
{SEC_CORE1_BITMAP_HIGH, "SEC_CORE1_BITMAP_HIGH ", 0x3158, 0x3FFF, 0x3FFF, 0x3FFF},
{SEC_CORE2_BITMAP_LOW, "SEC_CORE2_BITMAP_LOW ",
0x315c, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
{SEC_CORE2_BITMAP_HIGH, "SEC_CORE2_BITMAP_HIGH ", 0x3160, 0x3FFF, 0x3FFF, 0x3FFF},
{SEC_CORE3_BITMAP_LOW, "SEC_CORE3_BITMAP_LOW ",
0x3164, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
{SEC_CORE3_BITMAP_HIGH, "SEC_CORE3_BITMAP_HIGH ", 0x3168, 0x3FFF, 0x3FFF, 0x3FFF},
{SEC_CORE4_BITMAP_LOW, "SEC_CORE4_BITMAP_LOW ",
0x316c, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
{SEC_CORE4_BITMAP_HIGH, "SEC_CORE4_BITMAP_HIGH ", 0x3170, 0x3FFF, 0x3FFF, 0x3FFF},
};
static const struct qm_dev_alg sec_dev_algs[] = { {
@@ -838,6 +861,26 @@ static int sec_regs_show(struct seq_file *s, void *unused)
DEFINE_SHOW_ATTRIBUTE(sec_regs);
static int sec_cap_regs_show(struct seq_file *s, void *unused)
{
struct hisi_qm *qm = s->private;
u32 i, size;
size = qm->cap_tables.qm_cap_size;
for (i = 0; i < size; i++)
seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.qm_cap_table[i].name,
qm->cap_tables.qm_cap_table[i].cap_val);
size = qm->cap_tables.dev_cap_size;
for (i = 0; i < size; i++)
seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.dev_cap_table[i].name,
qm->cap_tables.dev_cap_table[i].cap_val);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(sec_cap_regs);
static int sec_core_debug_init(struct hisi_qm *qm)
{
struct dfx_diff_registers *sec_regs = qm->debug.acc_diff_regs;
@@ -872,6 +915,9 @@ static int sec_core_debug_init(struct hisi_qm *qm)
tmp_d, data, &sec_atomic64_ops);
}
debugfs_create_file("cap_regs", CAP_FILE_PERMISSION,
qm->debug.debug_root, qm, &sec_cap_regs_fops);
return 0;
}
@@ -1085,18 +1131,20 @@ static int sec_pre_store_cap_reg(struct hisi_qm *qm)
struct pci_dev *pdev = qm->pdev;
size_t i, size;
size = ARRAY_SIZE(sec_pre_store_caps);
size = ARRAY_SIZE(sec_cap_query_info);
sec_cap = devm_kzalloc(&pdev->dev, sizeof(*sec_cap) * size, GFP_KERNEL);
if (!sec_cap)
return -ENOMEM;
for (i = 0; i < size; i++) {
sec_cap[i].type = sec_pre_store_caps[i];
sec_cap[i].cap_val = hisi_qm_get_hw_info(qm, sec_basic_info,
sec_pre_store_caps[i], qm->cap_ver);
sec_cap[i].type = sec_cap_query_info[i].type;
sec_cap[i].name = sec_cap_query_info[i].name;
sec_cap[i].cap_val = hisi_qm_get_cap_value(qm, sec_cap_query_info,
i, qm->cap_ver);
}
qm->cap_tables.dev_cap_table = sec_cap;
qm->cap_tables.dev_cap_size = size;
return 0;
}
@@ -1146,8 +1194,7 @@ static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
hisi_qm_uninit(qm);
return ret;
}
alg_msk = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH_IDX, SEC_DEV_ALG_BITMAP_LOW_IDX);
alg_msk = sec_get_alg_bitmap(qm, SEC_ALG_BITMAP_HIGH, SEC_ALG_BITMAP_LOW);
ret = hisi_qm_set_algs(qm, alg_msk, sec_dev_algs, ARRAY_SIZE(sec_dev_algs));
if (ret) {
pci_err(qm->pdev, "Failed to set sec algs!\n");