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drm/amd/display: Enable DCE12 support

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This wires DCE12 support into DC and enables it.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
2017-06-15 16:20:24 -04:00
parent b8fdfcc6a9
commit 2c8ad2d5a2
44 changed files with 1143 additions and 8 deletions
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23
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
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@@ -888,6 +888,10 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
struct dc_interrupt_params int_params = {0};
int r;
int i;
unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
if (adev->asic_type == CHIP_VEGA10)
client_id = AMDGPU_IH_CLIENTID_DCE;
int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
@@ -904,7 +908,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
/* Use VBLANK interrupt */
for (i = 1; i <= adev->mode_info.num_crtc; i++) {
r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->crtc_irq);
r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
if (r) {
DRM_ERROR("Failed to add crtc irq id!\n");
@@ -927,7 +931,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
/* Use GRPH_PFLIP interrupt */
for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
if (r) {
DRM_ERROR("Failed to add page flip irq id!\n");
return r;
@@ -948,8 +952,8 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
}
/* HPD */
r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A,
&adev->hpd_irq);
r = amdgpu_irq_add_id(adev, client_id,
VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
if (r) {
DRM_ERROR("Failed to add hpd irq id!\n");
return r;
@@ -1119,6 +1123,9 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
case CHIP_POLARIS11:
case CHIP_POLARIS10:
case CHIP_POLARIS12:
#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
case CHIP_VEGA10:
#endif
if (dce110_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
return -1;
@@ -1312,6 +1319,7 @@ static const struct amdgpu_display_funcs dm_display_funcs = {
};
#if defined(CONFIG_DEBUG_KERNEL_DC)
static ssize_t s3_debug_store(
@@ -1384,6 +1392,13 @@ static int dm_early_init(void *handle)
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
case CHIP_VEGA10:
adev->mode_info.num_crtc = 6;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
#endif
default:
DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
return -EINVAL;