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drm/amdgpu: ensure no_hw_access is visible before MMIO

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Add a full memory barrier after clearing no_hw_access in
amdgpu_device_mode1_reset() so subsequent PCI state restore
access cannot observe stale state on other CPUs.

Fixes: 7edb503fe4 ("drm/amd/pm: Disable MMIO access during SMU Mode 1 reset")
Signed-off-by: Perry Yuan <perry.yuan@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Perry Yuan
2026-01-28 13:54:31 +08:00
committed by Alex Deucher
parent 3cc9398a9e
commit 31b153315b
1 changed files with 3 additions and 0 deletions
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3
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
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@@ -5733,6 +5733,9 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
/* enable mmio access after mode 1 reset completed */
adev->no_hw_access = false;
/* ensure no_hw_access is updated before we access hw */
smp_mb();
amdgpu_device_load_pci_state(adev->pdev);
ret = amdgpu_psp_wait_for_bootloader(adev);
if (ret)