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drm/i915: Rename I915_CACHE_MLC_LLC to L3_LLC for Ivybridge

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MLC_LLC was never validated for Sandybridge and was superseded by a new
level of cacheing for the GPU in Ivybridge. Update our names to be
consistent with usage, and in the process stop setting the unwanted bit
on Sandybridge.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: s/BUG/WARN_ON(1) bikeshed.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Chris Wilson
2013-08-06 13:17:02 +01:00
committed by Daniel Vetter
parent ad8d270c21
commit 350ec881d9
4 changed files with 38 additions and 12 deletions
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7
drivers/gpu/drm/i915/i915_drv.h
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@@ -449,8 +449,11 @@ struct intel_device_info {
enum i915_cache_level {
I915_CACHE_NONE = 0,
I915_CACHE_LLC,
I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
caches, eg sampler/render caches, and the
large Last-Level-Cache. LLC is coherent with
the CPU, but L3 is only visible to the GPU. */
};
typedef uint32_t gen6_gtt_pte_t;