mirror of
https://github.com/torvalds/linux.git
synced 2026-04-24 17:42:27 -04:00
Merge drm/drm-next into drm-misc-next
Kickstart 6.14 cycle. Signed-off-by: Maxime Ripard <mripard@kernel.org>
This commit is contained in:
Maxime Ripard
@@ -1308,6 +1308,29 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
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DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
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adev->dm.dmcub_fw_version);
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/* Keeping sanity checks off if
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* DCN31 >= 4.0.59.0
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* DCN314 >= 8.0.16.0
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* Otherwise, turn on sanity checks
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*/
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switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
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case IP_VERSION(3, 1, 2):
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case IP_VERSION(3, 1, 3):
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if (adev->dm.dmcub_fw_version &&
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adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
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adev->dm.dmcub_fw_version < DMUB_FW_VERSION(4, 0, 59))
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adev->dm.dc->debug.sanity_checks = true;
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break;
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case IP_VERSION(3, 1, 4):
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if (adev->dm.dmcub_fw_version &&
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adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
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adev->dm.dmcub_fw_version < DMUB_FW_VERSION(8, 0, 16))
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adev->dm.dc->debug.sanity_checks = true;
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break;
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default:
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break;
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}
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return 0;
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}
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@@ -3171,8 +3194,7 @@ static int dm_resume(struct amdgpu_ip_block *ip_block)
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struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
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enum dc_connection_type new_connection_type = dc_connection_none;
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struct dc_state *dc_state;
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int i, r, j, ret;
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bool need_hotplug = false;
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int i, r, j;
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struct dc_commit_streams_params commit_params = {};
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if (dm->dc->caps.ips_support) {
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@@ -3361,23 +3383,16 @@ static int dm_resume(struct amdgpu_ip_block *ip_block)
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aconnector->mst_root)
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continue;
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ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true);
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if (ret < 0) {
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dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
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aconnector->dc_link);
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need_hotplug = true;
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}
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drm_dp_mst_topology_queue_probe(&aconnector->mst_mgr);
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}
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drm_connector_list_iter_end(&iter);
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if (need_hotplug)
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drm_kms_helper_hotplug_event(ddev);
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amdgpu_dm_irq_resume_late(adev);
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amdgpu_dm_smu_write_watermarks_table(adev);
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drm_kms_helper_hotplug_event(ddev);
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return 0;
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}
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@@ -4654,7 +4669,12 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
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if (!rc)
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DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
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} else {
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rc = dc_link_set_backlight_level(link, brightness, 0);
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struct set_backlight_level_params backlight_level_params = { 0 };
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backlight_level_params.backlight_pwm_u16_16 = brightness;
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backlight_level_params.transition_time_in_ms = 0;
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rc = dc_link_set_backlight_level(link, &backlight_level_params);
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if (!rc)
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DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
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}
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@@ -6799,7 +6819,7 @@ create_stream_for_sink(struct drm_connector *connector,
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if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22)
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tf = TRANSFER_FUNC_GAMMA_22;
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mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
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aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
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aconnector->sr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
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}
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finish:
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@@ -7332,10 +7352,15 @@ create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
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const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
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int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
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enum dc_status dc_result = DC_OK;
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uint8_t bpc_limit = 6;
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if (!dm_state)
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return NULL;
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if (aconnector->dc_link->connector_signal == SIGNAL_TYPE_HDMI_TYPE_A ||
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aconnector->dc_link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
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bpc_limit = 8;
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do {
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stream = create_stream_for_sink(connector, drm_mode,
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dm_state, old_stream,
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@@ -7356,11 +7381,12 @@ create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
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dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
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if (dc_result != DC_OK) {
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DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
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DRM_DEBUG_KMS("Mode %dx%d (clk %d) pixel_encoding:%s color_depth:%s failed validation -- %s\n",
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drm_mode->hdisplay,
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drm_mode->vdisplay,
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drm_mode->clock,
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dc_result,
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dc_pixel_encoding_to_str(stream->timing.pixel_encoding),
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dc_color_depth_to_str(stream->timing.display_color_depth),
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dc_status_to_str(dc_result));
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dc_stream_release(stream);
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@@ -7368,10 +7394,13 @@ create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
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requested_bpc -= 2; /* lower bpc to retry validation */
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}
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} while (stream == NULL && requested_bpc >= 6);
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} while (stream == NULL && requested_bpc >= bpc_limit);
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if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
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DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
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if ((dc_result == DC_FAIL_ENC_VALIDATE ||
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dc_result == DC_EXCEED_DONGLE_CAP) &&
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!aconnector->force_yuv420_output) {
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DRM_DEBUG_KMS("%s:%d Retry forcing yuv420 encoding\n",
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__func__, __LINE__);
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aconnector->force_yuv420_output = true;
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stream = create_validate_stream_for_sink(aconnector, drm_mode,
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@@ -8894,6 +8923,56 @@ static void amdgpu_dm_update_cursor(struct drm_plane *plane,
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}
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}
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static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach,
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const struct dm_crtc_state *acrtc_state,
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const u64 current_ts)
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{
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struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
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struct replay_settings *pr = &acrtc_state->stream->link->replay_settings;
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struct amdgpu_dm_connector *aconn =
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(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
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if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
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if (pr->config.replay_supported && !pr->replay_feature_enabled)
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amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);
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else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED &&
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!psr->psr_feature_enabled)
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if (!aconn->disallow_edp_enter_psr)
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amdgpu_dm_link_setup_psr(acrtc_state->stream);
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}
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/* Decrement skip count when SR is enabled and we're doing fast updates. */
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if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
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(psr->psr_feature_enabled || pr->config.replay_supported)) {
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if (aconn->sr_skip_count > 0)
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aconn->sr_skip_count--;
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/* Allow SR when skip count is 0. */
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acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count;
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/*
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* If sink supports PSR SU/Panel Replay, there is no need to rely on
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* a vblank event disable request to enable PSR/RP. PSR SU/RP
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* can be enabled immediately once OS demonstrates an
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* adequate number of fast atomic commits to notify KMD
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* of update events. See `vblank_control_worker()`.
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*/
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if (acrtc_attach->dm_irq_params.allow_sr_entry &&
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#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
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!amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
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#endif
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(current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) {
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if (pr->replay_feature_enabled && !pr->replay_allow_active)
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amdgpu_dm_replay_enable(acrtc_state->stream, true);
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if (psr->psr_version >= DC_PSR_VERSION_SU_1 &&
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!psr->psr_allow_active && !aconn->disallow_edp_enter_psr)
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amdgpu_dm_psr_enable(acrtc_state->stream);
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}
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} else {
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acrtc_attach->dm_irq_params.allow_sr_entry = false;
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}
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}
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static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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struct drm_device *dev,
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struct amdgpu_display_manager *dm,
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@@ -9047,7 +9126,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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* during the PSR-SU was disabled.
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*/
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if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
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acrtc_attach->dm_irq_params.allow_psr_entry &&
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acrtc_attach->dm_irq_params.allow_sr_entry &&
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#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
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!amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
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#endif
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@@ -9222,9 +9301,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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bundle->stream_update.abm_level = &acrtc_state->abm_level;
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mutex_lock(&dm->dc_lock);
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if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
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acrtc_state->stream->link->psr_settings.psr_allow_active)
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amdgpu_dm_psr_disable(acrtc_state->stream);
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if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
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if (acrtc_state->stream->link->replay_settings.replay_allow_active)
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amdgpu_dm_replay_disable(acrtc_state->stream);
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if (acrtc_state->stream->link->psr_settings.psr_allow_active)
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amdgpu_dm_psr_disable(acrtc_state->stream);
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}
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mutex_unlock(&dm->dc_lock);
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/*
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@@ -9265,57 +9347,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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dm_update_pflip_irq_state(drm_to_adev(dev),
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acrtc_attach);
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if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
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if (acrtc_state->stream->link->replay_settings.config.replay_supported &&
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!acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
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struct amdgpu_dm_connector *aconn =
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(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
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amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);
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} else if (acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
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!acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
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struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *)
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acrtc_state->stream->dm_stream_context;
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if (!aconn->disallow_edp_enter_psr)
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amdgpu_dm_link_setup_psr(acrtc_state->stream);
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}
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}
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/* Decrement skip count when PSR is enabled and we're doing fast updates. */
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if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
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acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
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struct amdgpu_dm_connector *aconn =
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(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
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if (aconn->psr_skip_count > 0)
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aconn->psr_skip_count--;
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/* Allow PSR when skip count is 0. */
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acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
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/*
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* If sink supports PSR SU, there is no need to rely on
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* a vblank event disable request to enable PSR. PSR SU
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* can be enabled immediately once OS demonstrates an
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* adequate number of fast atomic commits to notify KMD
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* of update events. See `vblank_control_worker()`.
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*/
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if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
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acrtc_attach->dm_irq_params.allow_psr_entry &&
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#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
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!amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
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#endif
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!acrtc_state->stream->link->psr_settings.psr_allow_active &&
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!aconn->disallow_edp_enter_psr &&
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(timestamp_ns -
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acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
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500000000)
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amdgpu_dm_psr_enable(acrtc_state->stream);
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} else {
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acrtc_attach->dm_irq_params.allow_psr_entry = false;
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}
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amdgpu_dm_enable_self_refresh(acrtc_attach, acrtc_state, timestamp_ns);
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mutex_unlock(&dm->dc_lock);
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}
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@@ -9448,6 +9480,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
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bool mode_set_reset_required = false;
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u32 i;
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struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count};
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bool set_backlight_level = false;
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/* Disable writeback */
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for_each_old_connector_in_state(state, connector, old_con_state, i) {
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@@ -9567,6 +9600,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
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acrtc->hw_mode = new_crtc_state->mode;
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crtc->hwmode = new_crtc_state->mode;
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mode_set_reset_required = true;
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set_backlight_level = true;
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} else if (modereset_required(new_crtc_state)) {
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drm_dbg_atomic(dev,
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"Atomic commit: RESET. crtc id %d:[%p]\n",
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@@ -9618,6 +9652,19 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
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acrtc->otg_inst = status->primary_otg_inst;
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}
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}
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/* During boot up and resume the DC layer will reset the panel brightness
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* to fix a flicker issue.
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* It will cause the dm->actual_brightness is not the current panel brightness
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* level. (the dm->brightness is the correct panel level)
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* So we set the backlight level with dm->brightness value after set mode
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*/
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if (set_backlight_level) {
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for (i = 0; i < dm->num_of_edps; i++) {
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if (dm->backlight_dev[i])
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amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
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}
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}
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}
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static void dm_set_writeback(struct amdgpu_display_manager *dm,
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@@ -12086,7 +12133,7 @@ static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
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break;
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}
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while (j < EDID_LENGTH) {
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while (j < EDID_LENGTH - sizeof(struct amd_vsdb_block)) {
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struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
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unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
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