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crypto: qat - expand CSR operations for QAT GEN4 devices

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Extend the CSR operations for QAT GEN4 devices to allow saving and
restoring the rings state.

The new operations will be used as a building block for implementing the
state save and restore of Virtual Functions necessary for VM live
migration.

This adds the following operations:
 - read ring status register
 - read ring underflow/overflow status register
 - read ring nearly empty status register
 - read ring nearly full status register
 - read ring full status register
 - read ring complete status register
 - read ring exception status register
 - read/write ring exception interrupt mask register
 - read ring configuration register
 - read ring base register
 - read/write ring interrupt enable register
 - read ring interrupt flag register
 - read/write ring interrupt source select register
 - read ring coalesced interrupt enable register
 - read ring coalesced interrupt control register
 - read ring flag and coalesced interrupt enable register
 - read ring service arbiter enable register
 - get ring coalesced interrupt control enable mask

Signed-off-by: Siming Wan <siming.wan@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Xin Zeng <xin.zeng@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Siming Wan
2024-03-06 21:58:51 +08:00
committed by Herbert Xu
parent 84058ffb91
commit 3fa1057e35
3 changed files with 249 additions and 1 deletions
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27
drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
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@@ -150,22 +150,49 @@ struct adf_hw_csr_ops {
u32 ring);
void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
u32 ring, u32 value);
u32 (*read_csr_stat)(void __iomem *csr_base_addr, u32 bank);
u32 (*read_csr_uo_stat)(void __iomem *csr_base_addr, u32 bank);
u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);
u32 (*read_csr_ne_stat)(void __iomem *csr_base_addr, u32 bank);
u32 (*read_csr_nf_stat)(void __iomem *csr_base_addr, u32 bank);
u32 (*read_csr_f_stat)(void __iomem *csr_base_addr, u32 bank);
u32 (*read_csr_c_stat)(void __iomem *csr_base_addr, u32 bank);
u32 (*read_csr_exp_stat)(void __iomem *csr_base_addr, u32 bank);
u32 (*read_csr_exp_int_en)(void __iomem *csr_base_addr, u32 bank);
void (*write_csr_exp_int_en)(void __iomem *csr_base_addr, u32 bank,
u32 value);
u32 (*read_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,
u32 ring);
void (*write_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,
u32 ring, u32 value);
dma_addr_t (*read_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,
u32 ring);
void (*write_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,
u32 ring, dma_addr_t addr);
u32 (*read_csr_int_en)(void __iomem *csr_base_addr, u32 bank);
void (*write_csr_int_en)(void __iomem *csr_base_addr, u32 bank,
u32 value);
u32 (*read_csr_int_flag)(void __iomem *csr_base_addr, u32 bank);
void (*write_csr_int_flag)(void __iomem *csr_base_addr, u32 bank,
u32 value);
u32 (*read_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);
void (*write_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);
void (*write_csr_int_srcsel_w_val)(void __iomem *csr_base_addr,
u32 bank, u32 value);
u32 (*read_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank);
void (*write_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank,
u32 value);
u32 (*read_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank);
void (*write_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank,
u32 value);
u32 (*read_csr_int_flag_and_col)(void __iomem *csr_base_addr,
u32 bank);
void (*write_csr_int_flag_and_col)(void __iomem *csr_base_addr,
u32 bank, u32 value);
u32 (*read_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank);
void (*write_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank,
u32 value);
u32 (*get_int_col_ctl_enable_mask)(void);
};
struct adf_cfg_device_data;