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Merge drm/drm-next into drm-xe-next
Backmerging to bring in 7.00-rc3. Important ahead GPU SVM merging THP support. Signed-off-by: Matthew Brost <matthew.brost@intel.com>
This commit is contained in:
Matthew Brost
687
Documentation/gpu/amdgpu/amd_overview_block.svg
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687
Documentation/gpu/amdgpu/amd_overview_block.svg
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id="tspan14">DCN</tspan></text>
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||||
</g>
|
||||
</g>
|
||||
</svg>
|
||||
|
After Width: | Height: | Size: 30 KiB |
@@ -30,6 +30,15 @@ we have a dedicated glossary for Display Core at
|
||||
CP
|
||||
Command Processor
|
||||
|
||||
CPC
|
||||
Command Processor Compute
|
||||
|
||||
CPF
|
||||
Command Processor Fetch
|
||||
|
||||
CPG
|
||||
Command Processor Graphics
|
||||
|
||||
CPLIB
|
||||
Content Protection Library
|
||||
|
||||
@@ -78,6 +87,9 @@ we have a dedicated glossary for Display Core at
|
||||
GMC
|
||||
Graphic Memory Controller
|
||||
|
||||
GPR
|
||||
General Purpose Register
|
||||
|
||||
GPUVM
|
||||
GPU Virtual Memory. This is the GPU's MMU. The GPU supports multiple
|
||||
virtual address spaces that can be in flight at any given time. These
|
||||
@@ -92,9 +104,15 @@ we have a dedicated glossary for Display Core at
|
||||
table for use by the kernel driver or into per process GPUVM page tables
|
||||
for application usage.
|
||||
|
||||
GWS
|
||||
Global Wave Sync
|
||||
|
||||
IH
|
||||
Interrupt Handler
|
||||
|
||||
IV
|
||||
Interrupt Vector
|
||||
|
||||
HQD
|
||||
Hardware Queue Descriptor
|
||||
|
||||
@@ -143,15 +161,24 @@ we have a dedicated glossary for Display Core at
|
||||
PA
|
||||
Primitive Assembler / Physical Address
|
||||
|
||||
PDE
|
||||
Page Directory Entry
|
||||
|
||||
PFP
|
||||
Pre-Fetch Parser (Graphics)
|
||||
|
||||
PPLib
|
||||
PowerPlay Library - PowerPlay is the power management component.
|
||||
|
||||
PRT
|
||||
Partially Resident Texture (also known as sparse residency)
|
||||
|
||||
PSP
|
||||
Platform Security Processor
|
||||
|
||||
PTE
|
||||
Page Table Entry
|
||||
|
||||
RB
|
||||
Render Backends. Some people called it ROPs.
|
||||
|
||||
@@ -206,12 +233,33 @@ we have a dedicated glossary for Display Core at
|
||||
TC
|
||||
Texture Cache
|
||||
|
||||
TCP (AMDGPU)
|
||||
Texture Cache per Pipe. Even though the name "Texture" is part of this
|
||||
acronym, the TCP represents the path to memory shaders; i.e., it is not
|
||||
related to texture. The name is a leftover from older designs where shader
|
||||
stages had different cache designs; it refers to the L1 cache in older
|
||||
architectures.
|
||||
|
||||
TMR
|
||||
Trusted Memory Region
|
||||
|
||||
TMZ
|
||||
Trusted Memory Zone
|
||||
|
||||
TOC
|
||||
Table of Contents
|
||||
|
||||
UMC
|
||||
Unified Memory Controller
|
||||
|
||||
UMSCH
|
||||
User Mode Scheduler
|
||||
|
||||
UTC (AMDGPU)
|
||||
Unified Translation Cache. UTC is equivalent to TLB. You might see a
|
||||
variation of this acronym with L at the end, i.e., UTCL followed by a
|
||||
number; L means the cache level (e.g., UTCL1 and UTCL2).
|
||||
|
||||
UVD
|
||||
Unified Video Decoder
|
||||
|
||||
|
||||
@@ -16,3 +16,6 @@ Ryzen AI 300 series, Strix Point, 3.5.0, 11.5.0, 4.0.5, 6.1.0, 14.0.0, 14.0.0
|
||||
Ryzen AI 330 series, Krackan Point, 3.6.0, 11.5.3, 4.0.5, 6.1.3, 14.0.5, 14.0.5
|
||||
Ryzen AI 350 series, Krackan Point, 3.5.0, 11.5.2, 4.0.5, 6.1.2, 14.0.4, 14.0.4
|
||||
Ryzen AI Max 300 series, Strix Halo, 3.5.1, 11.5.1, 4.0.6, 6.1.1, 14.0.1, 14.0.1
|
||||
Ryzen AI 9 475 / 470 / 465, Gorgon Point, 3.5.0, 11.5.0, 4.0.5, 6.1.0, 14.0.0, 14.0.0
|
||||
Ryzen AI 7 450, Gorgon Point, 3.5.0, 11.5.2, 4.0.5, 6.1.2, 14.0.4, 14.0.4
|
||||
Ryzen AI 5 440 / 435, Gorgon Point, 3.6.0, 11.5.3, 4.0.5, 6.1.3, 14.0.5, 14.0.5
|
||||
|
||||
|
@@ -221,9 +221,6 @@ consider asking on the amd-gfx mailing list and update this page.
|
||||
TMDS
|
||||
Transition-Minimized Differential Signaling
|
||||
|
||||
TMZ
|
||||
Trusted Memory Zone
|
||||
|
||||
TTU
|
||||
Time to Underflow
|
||||
|
||||
|
||||
@@ -77,6 +77,37 @@ VCN (Video Core Next)
|
||||
decode. It's exposed to userspace for user mode drivers (VA-API,
|
||||
OpenMAX, etc.)
|
||||
|
||||
It is important to note that these blocks can interact with each other. The
|
||||
picture below illustrates some of the components and their interconnection:
|
||||
|
||||
.. kernel-figure:: amd_overview_block.svg
|
||||
|
||||
In the diagram, memory-related blocks are shown in green. Notice that specific
|
||||
IPs have a green square that represents a small hardware block named 'hub',
|
||||
which is responsible for interfacing with memory. All memory hubs are connected
|
||||
in the UMCs, which in turn are connected to memory blocks. As a note,
|
||||
pre-vega devices have a dedicated block for the Graphic Memory Controller
|
||||
(GMC), which was replaced by UMC and hubs in new architectures. In the driver
|
||||
code, you can identify this component by looking for the suffix hub, for
|
||||
example: gfxhub, dchub, mmhub, vmhub, etc. Keep in mind that the component's
|
||||
interaction with the memory block may vary across architectures. For example,
|
||||
on Navi and newer, GC and SDMA are both attached to GCHUB; on pre-Navi, SDMA
|
||||
goes through MMHUB; VCN, JPEG, and VPE go through MMHUB; DCN goes through
|
||||
DCHUB.
|
||||
|
||||
There is some protection for certain memory elements, and the PSP plays an
|
||||
essential role in this area. When a specific firmware is loaded into memory,
|
||||
the PSP takes steps to ensure it has a valid signature. It also stores firmware
|
||||
images in a protected memory area named Trusted Memory Area (TMR), so the OS or
|
||||
driver can't corrupt them at runtime. Another use of PSP is to support Trusted
|
||||
Applications (TA), which are basically small applications that run on the
|
||||
trusted processor and handles a trusted operation (e.g., HDCP). PSP is also
|
||||
used for encrypted memory for content protection via Trusted Memory Zone (TMZ).
|
||||
|
||||
Another critical IP is the SMU. It handles reset distribution, as well as
|
||||
clock, thermal, and power management for all IPs on the SoC. SMU also helps to
|
||||
balance performance and power consumption.
|
||||
|
||||
.. _pipes-and-queues-description:
|
||||
|
||||
GFX, Compute, and SDMA Overall Behavior
|
||||
|
||||
@@ -128,3 +128,29 @@ smartshift_bias
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
|
||||
:doc: smartshift_bias
|
||||
|
||||
UMA Carveout
|
||||
============
|
||||
|
||||
Some versions of Atom ROM expose available options for the VRAM carveout sizes,
|
||||
and allow changes to the carveout size via the ATCS function code 0xA on supported
|
||||
BIOS implementations.
|
||||
|
||||
For those platforms, users can use the following files under uma/ to set the
|
||||
carveout size, in a way similar to what Windows users can do in the "Tuning"
|
||||
tab in AMD Adrenalin.
|
||||
|
||||
Note that for BIOS implementations that don't support this, these files will not
|
||||
be created at all.
|
||||
|
||||
uma/carveout_options
|
||||
--------------------
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
|
||||
:doc: uma/carveout_options
|
||||
|
||||
uma/carveout
|
||||
--------------------
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
|
||||
:doc: uma/carveout
|
||||
|
||||
654
Documentation/gpu/amdgpu/enforce_isolation.svg
Normal file
654
Documentation/gpu/amdgpu/enforce_isolation.svg
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(producer) to be executed by the GPU (consumer). The requested operations in
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the buffer are called **Command Packets**, which can be summarized as a
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The component that acts as the front end between the CPU and the GPU is called
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**Command Processor (CP)**. This component is responsible for providing greater
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Graphics (GFX) and Compute Microcontrollers
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-------------------------------------------
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After Width: | Height: | Size: 21 KiB |
@@ -8,6 +8,7 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures.
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.. toctree::
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driver-core
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ring-buffer
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amd-hardware-list-info
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module-parameters
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gc/index
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707
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After Width: | Height: | Size: 36 KiB |
@@ -1,3 +1,4 @@
|
||||
.. _amdgpu-process-isolation:
|
||||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
=========================
|
||||
|
||||
95
Documentation/gpu/amdgpu/ring-buffer.rst
Normal file
95
Documentation/gpu/amdgpu/ring-buffer.rst
Normal file
@@ -0,0 +1,95 @@
|
||||
=============
|
||||
Ring Buffer
|
||||
=============
|
||||
|
||||
To handle communication between user space and kernel space, AMD GPUs use a
|
||||
ring buffer design to feed the engines (GFX, Compute, SDMA, UVD, VCE, VCN, VPE,
|
||||
etc.). See the figure below that illustrates how this communication works:
|
||||
|
||||
.. kernel-figure:: ring_buffers.svg
|
||||
|
||||
Ring buffers in the amdgpu work as a producer-consumer model, where userspace
|
||||
acts as the producer, constantly filling the ring buffer with GPU commands to
|
||||
be executed. Meanwhile, the GPU retrieves the information from the ring, parses
|
||||
it, and distributes the specific set of instructions between the different
|
||||
amdgpu blocks.
|
||||
|
||||
Notice from the diagram that the ring has a Read Pointer (rptr), which
|
||||
indicates where the engine is currently reading packets from the ring, and a
|
||||
Write Pointer (wptr), which indicates how many packets software has added to
|
||||
the ring. When the rptr and wptr are equal, the ring is idle. When software
|
||||
adds packets to the ring, it updates the wptr, this causes the engine to start
|
||||
fetching and processing packets. As the engine processes packets, the rptr gets
|
||||
updates until the rptr catches up to the wptr and they are equal again.
|
||||
|
||||
Usually, ring buffers in the driver have a limited size (search for occurrences
|
||||
of `amdgpu_ring_init()`). One of the reasons for the small ring buffer size is
|
||||
that CP (Command Processor) is capable of following addresses inserted into the
|
||||
ring; this is illustrated in the image by the reference to the IB (Indirect
|
||||
Buffer). The IB gives userspace the possibility to have an area in memory that
|
||||
CP can read and feed the hardware with extra instructions.
|
||||
|
||||
All ASICs pre-GFX11 use what is called a kernel queue, which means
|
||||
the ring is allocated in kernel space and has some restrictions, such as not
|
||||
being able to be :ref:`preempted directly by the scheduler<amdgpu-mes>`. GFX11
|
||||
and newer support kernel queues, but also provide a new mechanism named
|
||||
:ref:`user queues<amdgpu-userq>`, where the queue is moved to the user space
|
||||
and can be mapped and unmapped via the scheduler. In practice, both queues
|
||||
insert user-space-generated GPU commands from different jobs into the requested
|
||||
component ring.
|
||||
|
||||
Enforce Isolation
|
||||
=================
|
||||
|
||||
.. note:: After reading this section, you might want to check the
|
||||
:ref:`Process Isolation<amdgpu-process-isolation>` page for more details.
|
||||
|
||||
Before examining the Enforce Isolation mechanism in the ring buffer context, it
|
||||
is helpful to briefly discuss how instructions from the ring buffer are
|
||||
processed in the graphics pipeline. Let’s expand on this topic by checking the
|
||||
diagram below that illustrates the graphics pipeline:
|
||||
|
||||
.. kernel-figure:: gfx_pipeline_seq.svg
|
||||
|
||||
In terms of executing instructions, the GFX pipeline follows the sequence:
|
||||
Shader Export (SX), Geometry Engine (GE), Shader Process or Input (SPI), Scan
|
||||
Converter (SC), Primitive Assembler (PA), and cache manipulation (which may
|
||||
vary across ASICs). Another common way to describe the pipeline is to use Pixel
|
||||
Shader (PS), raster, and Vertex Shader (VS) to symbolize the two shader stages.
|
||||
Now, with this pipeline in mind, let's assume that Job B causes a hang issue,
|
||||
but Job C's instruction might already be executing, leading developers to
|
||||
incorrectly identify Job C as the problematic one. This problem can be
|
||||
mitigated on multiple levels; the diagram below illustrates how to minimize
|
||||
part of this problem:
|
||||
|
||||
.. kernel-figure:: no_enforce_isolation.svg
|
||||
|
||||
Note from the diagram that there is no guarantee of order or a clear separation
|
||||
between instructions, which is not a problem most of the time, and is also good
|
||||
for performance. Furthermore, notice some circles between jobs in the diagram
|
||||
that represent a **fence wait** used to avoid overlapping work in the ring. At
|
||||
the end of the fence, a cache flush occurs, ensuring that when the next job
|
||||
starts, it begins in a clean state and, if issues arise, the developer can
|
||||
pinpoint the problematic process more precisely.
|
||||
|
||||
To increase the level of isolation between jobs, there is the "Enforce
|
||||
Isolation" method described in the picture below:
|
||||
|
||||
.. kernel-figure:: enforce_isolation.svg
|
||||
|
||||
As shown in the diagram, enforcing isolation introduces ordering between
|
||||
submissions, since the access to GFX/Compute is serialized, think about it as
|
||||
single process at a time mode for gfx/compute. Notice that this approach has a
|
||||
significant performance impact, as it allows only one job to submit commands at
|
||||
a time. However, this option can help pinpoint the job that caused the problem.
|
||||
Although enforcing isolation improves the situation, it does not fully resolve
|
||||
the issue of precisely pinpointing bad jobs, since isolation might mask the
|
||||
problem. In summary, identifying which job caused the issue may not be precise,
|
||||
but enforcing isolation might help with the debugging.
|
||||
|
||||
Ring Operations
|
||||
===============
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
|
||||
:internal:
|
||||
|
||||
1633
Documentation/gpu/amdgpu/ring_buffers.svg
Normal file
1633
Documentation/gpu/amdgpu/ring_buffers.svg
Normal file
File diff suppressed because it is too large
Load Diff
|
After Width: | Height: | Size: 86 KiB |
@@ -1,3 +1,5 @@
|
||||
.. _amdgpu-userq:
|
||||
|
||||
==================
|
||||
User Mode Queues
|
||||
==================
|
||||
|
||||
@@ -26,10 +26,3 @@ GPU Driver Documentation
|
||||
panthor
|
||||
zynqmp
|
||||
nova/index
|
||||
|
||||
.. only:: subproject and html
|
||||
|
||||
Indices
|
||||
=======
|
||||
|
||||
* :ref:`genindex`
|
||||
|
||||
@@ -526,8 +526,14 @@ DRM GPUVM Function References
|
||||
DRM Buddy Allocator
|
||||
===================
|
||||
|
||||
DRM Buddy Function References
|
||||
-----------------------------
|
||||
Buddy Allocator Function References (GPU buddy)
|
||||
-----------------------------------------------
|
||||
|
||||
.. kernel-doc:: drivers/gpu/buddy.c
|
||||
:export:
|
||||
|
||||
DRM Buddy Specific Logging Function References
|
||||
----------------------------------------------
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/drm_buddy.c
|
||||
:export:
|
||||
|
||||
@@ -23,10 +23,3 @@ GPU Driver Developer's Guide
|
||||
implementation_guidelines
|
||||
todo
|
||||
rfc/index
|
||||
|
||||
.. only:: subproject and html
|
||||
|
||||
Indices
|
||||
=======
|
||||
|
||||
* :ref:`genindex`
|
||||
|
||||
@@ -41,8 +41,15 @@ trait [1] from the num crate.
|
||||
Having this generalization also helps with implementing a generic macro that
|
||||
automatically generates the corresponding mappings between a value and a number.
|
||||
|
||||
FromPrimitive support has been worked on in the past, but hasn't been followed
|
||||
since then [1].
|
||||
|
||||
There also have been considerations of ToPrimitive [2].
|
||||
|
||||
| Complexity: Beginner
|
||||
| Link: https://docs.rs/num/latest/num/trait.FromPrimitive.html
|
||||
| Link: https://lore.kernel.org/all/cover.1750689857.git.y.j3ms.n@gmail.com/ [1]
|
||||
| Link: https://rust-for-linux.zulipchat.com/#narrow/channel/288089-General/topic/Implement.20.60FromPrimitive.60.20trait.20.2B.20derive.20macro.20for.20nova-core/with/541971854 [2]
|
||||
|
||||
Generic register abstraction [REGA]
|
||||
-----------------------------------
|
||||
@@ -134,21 +141,6 @@ A `num` core kernel module is being designed to provide these operations.
|
||||
| Complexity: Intermediate
|
||||
| Contact: Alexandre Courbot
|
||||
|
||||
IRQ abstractions
|
||||
----------------
|
||||
|
||||
Rust abstractions for IRQ handling.
|
||||
|
||||
There is active ongoing work from Daniel Almeida [1] for the "core" abstractions
|
||||
to request IRQs.
|
||||
|
||||
Besides optional review and testing work, the required ``pci::Device`` code
|
||||
around those core abstractions needs to be worked out.
|
||||
|
||||
| Complexity: Intermediate
|
||||
| Link: https://lore.kernel.org/lkml/20250122163932.46697-1-daniel.almeida@collabora.com/ [1]
|
||||
| Contact: Daniel Almeida
|
||||
|
||||
Page abstraction for foreign pages
|
||||
----------------------------------
|
||||
|
||||
@@ -161,40 +153,16 @@ There is active onging work from Abdiel Janulgue [1] and Lina [2].
|
||||
| Link: https://lore.kernel.org/linux-mm/20241119112408.779243-1-abdiel.janulgue@gmail.com/ [1]
|
||||
| Link: https://lore.kernel.org/rust-for-linux/20250202-rust-page-v1-0-e3170d7fe55e@asahilina.net/ [2]
|
||||
|
||||
Scatterlist / sg_table abstractions
|
||||
-----------------------------------
|
||||
|
||||
Rust abstractions for scatterlist / sg_table.
|
||||
|
||||
There is preceding work from Abdiel Janulgue, which hasn't made it to the
|
||||
mailing list yet.
|
||||
|
||||
| Complexity: Intermediate
|
||||
| Contact: Abdiel Janulgue
|
||||
|
||||
PCI MISC APIs
|
||||
-------------
|
||||
|
||||
Extend the existing PCI device / driver abstractions by SR-IOV, config space,
|
||||
capability, MSI API abstractions.
|
||||
Extend the existing PCI device / driver abstractions by SR-IOV, capability, MSI
|
||||
API abstractions.
|
||||
|
||||
SR-IOV [1] is work in progress.
|
||||
|
||||
| Complexity: Beginner
|
||||
|
||||
XArray bindings [XARR]
|
||||
----------------------
|
||||
|
||||
We need bindings for `xa_alloc`/`xa_alloc_cyclic` in order to generate the
|
||||
auxiliary device IDs.
|
||||
|
||||
| Complexity: Intermediate
|
||||
|
||||
Debugfs abstractions
|
||||
--------------------
|
||||
|
||||
Rust abstraction for debugfs APIs.
|
||||
|
||||
| Reference: Export GSP log buffers
|
||||
| Complexity: Intermediate
|
||||
| Link: https://lore.kernel.org/all/20251119-rust-pci-sriov-v1-0-883a94599a97@redhat.com/ [1]
|
||||
|
||||
GPU (general)
|
||||
=============
|
||||
@@ -233,7 +201,10 @@ Some possible options:
|
||||
- maple_tree
|
||||
- native Rust collections
|
||||
|
||||
There is work in progress for using drm_buddy [1].
|
||||
|
||||
| Complexity: Advanced
|
||||
| Link: https://lore.kernel.org/all/20251219203805.1246586-4-joelagnelf@nvidia.com/ [1]
|
||||
|
||||
Instance Memory
|
||||
---------------
|
||||
|
||||
@@ -506,6 +506,22 @@ Contact: Maxime Ripard <mripard@kernel.org>,
|
||||
|
||||
Level: Intermediate
|
||||
|
||||
Convert users of of_drm_find_bridge() to of_drm_find_and_get_bridge()
|
||||
---------------------------------------------------------------------
|
||||
|
||||
Taking a struct drm_bridge pointer requires getting a reference and putting
|
||||
it after disposing of the pointer. Most functions returning a struct
|
||||
drm_bridge pointer already call drm_bridge_get() to increment the refcount
|
||||
and their users have been updated to call drm_bridge_put() when
|
||||
appropriate. of_drm_find_bridge() does not get a reference and it has been
|
||||
deprecated in favor of of_drm_find_and_get_bridge() which does, but some
|
||||
users still need to be converted.
|
||||
|
||||
Contact: Maxime Ripard <mripard@kernel.org>,
|
||||
Luca Ceresoli <luca.ceresoli@bootlin.com>
|
||||
|
||||
Level: Intermediate
|
||||
|
||||
Core refactorings
|
||||
=================
|
||||
|
||||
|
||||
Reference in New Issue
Block a user