bybrooklyn/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-05 06:52:34 -04:00
Code Issues Packages Projects Releases Wiki Activity

drm/amd/dc: Add dc display driver (v2)

Browse Source 
Supported DCE versions: 8.0, 10.0, 11.0, 11.2

v2: rebase against 4.11

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland
2017-09-12 15:58:20 -04:00
committed by Alex Deucher
parent 9c5b2b0d40
commit 4562236b3b
315 changed files with 99491 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/gpu/drm/amd/display/dc/dce/Makefile Normal file
View File

@@ -0,0 +1,14 @@
#
# Makefile for common 'dce' logic
# HW object file under this folder follow similar pattern for HW programming
# - register offset and/or shift + mask stored in the dec_hw struct
# - register programming through common macros that look up register
# offset/shift/mask stored in dce_hw struct
DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \
dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o
AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
AMD_DISPLAY_FILES += $(AMD_DAL_DCE)

920
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c Normal file
View File

@@ -0,0 +1,920 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "reg_helper.h"
#include "dce_audio.h"
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"
#define DCE_AUD(audio)\
container_of(audio, struct dce_audio, base)
#define CTX \
aud->base.ctx
#define REG(reg)\
(aud->regs->reg)
#undef FN
#define FN(reg_name, field_name) \
aud->shifts->field_name, aud->masks->field_name
#define IX_REG(reg)\
ix ## reg
#define AZ_REG_READ(reg_name) \
read_indirect_azalia_reg(audio, IX_REG(reg_name))
#define AZ_REG_WRITE(reg_name, value) \
write_indirect_azalia_reg(audio, IX_REG(reg_name), value)
static void write_indirect_azalia_reg(struct audio *audio,
uint32_t reg_index,
uint32_t reg_data)
{
struct dce_audio *aud = DCE_AUD(audio);
/* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */
REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
AZALIA_ENDPOINT_REG_INDEX, reg_index);
/* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0,
AZALIA_ENDPOINT_REG_DATA, reg_data);
dm_logger_write(CTX->logger, LOG_HW_AUDIO,
"AUDIO:write_indirect_azalia_reg: index: %u data: %u\n",
reg_index, reg_data);
}
static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index)
{
struct dce_audio *aud = DCE_AUD(audio);
uint32_t value = 0;
/* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */
REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
AZALIA_ENDPOINT_REG_INDEX, reg_index);
/* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA);
dm_logger_write(CTX->logger, LOG_HW_AUDIO,
"AUDIO:read_indirect_azalia_reg: index: %u data: %u\n",
reg_index, value);
return value;
}
static bool is_audio_format_supported(
const struct audio_info *audio_info,
enum audio_format_code audio_format_code,
uint32_t *format_index)
{
uint32_t index;
uint32_t max_channe_index = 0;
bool found = false;
if (audio_info == NULL)
return found;
/* pass through whole array */
for (index = 0; index < audio_info->mode_count; index++) {
if (audio_info->modes[index].format_code == audio_format_code) {
if (found) {
/* format has multiply entries, choose one with
* highst number of channels */
if (audio_info->modes[index].channel_count >
audio_info->modes[max_channe_index].channel_count) {
max_channe_index = index;
}
} else {
/* format found, save it's index */
found = true;
max_channe_index = index;
}
}
}
/* return index */
if (found && format_index != NULL)
*format_index = max_channe_index;
return found;
}
/*For HDMI, calculate if specified sample rates can fit into a given timing */
static void check_audio_bandwidth_hdmi(
const struct audio_crtc_info *crtc_info,
uint32_t channel_count,
union audio_sample_rates *sample_rates)
{
uint32_t samples;
uint32_t h_blank;
bool limit_freq_to_48_khz = false;
bool limit_freq_to_88_2_khz = false;
bool limit_freq_to_96_khz = false;
bool limit_freq_to_174_4_khz = false;
/* For two channels supported return whatever sink support,unmodified*/
if (channel_count > 2) {
/* Based on HDMI spec 1.3 Table 7.5 */
if ((crtc_info->requested_pixel_clock <= 27000) &&
(crtc_info->v_active <= 576) &&
!(crtc_info->interlaced) &&
!(crtc_info->pixel_repetition == 2 ||
crtc_info->pixel_repetition == 4)) {
limit_freq_to_48_khz = true;
} else if ((crtc_info->requested_pixel_clock <= 27000) &&
(crtc_info->v_active <= 576) &&
(crtc_info->interlaced) &&
(crtc_info->pixel_repetition == 2)) {
limit_freq_to_88_2_khz = true;
} else if ((crtc_info->requested_pixel_clock <= 54000) &&
(crtc_info->v_active <= 576) &&
!(crtc_info->interlaced)) {
limit_freq_to_174_4_khz = true;
}
}
/* Also do some calculation for the available Audio Bandwidth for the
* 8 ch (i.e. for the Layout 1 => ch > 2)
*/
h_blank = crtc_info->h_total - crtc_info->h_active;
if (crtc_info->pixel_repetition)
h_blank *= crtc_info->pixel_repetition;
/*based on HDMI spec 1.3 Table 7.5 */
h_blank -= 58;
/*for Control Period */
h_blank -= 16;
samples = h_blank * 10;
/* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number
* of Audio samples per line multiplied by 10 - Layout 1)
*/
samples /= 32;
samples *= crtc_info->v_active;
/*Number of samples multiplied by 10, per second */
samples *= crtc_info->refresh_rate;
/*Number of Audio samples per second */
samples /= 10;
/* @todo do it after deep color is implemented
* 8xx - deep color bandwidth scaling
* Extra bandwidth is avaliable in deep color b/c link runs faster than
* pixel rate. This has the effect of allowing more tmds characters to
* be transmitted during blank
*/
switch (crtc_info->color_depth) {
case COLOR_DEPTH_888:
samples *= 4;
break;
case COLOR_DEPTH_101010:
samples *= 5;
break;
case COLOR_DEPTH_121212:
samples *= 6;
break;
default:
samples *= 4;
break;
}
samples /= 4;
/*check limitation*/
if (samples < 88200)
limit_freq_to_48_khz = true;
else if (samples < 96000)
limit_freq_to_88_2_khz = true;
else if (samples < 176400)
limit_freq_to_96_khz = true;
else if (samples < 192000)
limit_freq_to_174_4_khz = true;
if (sample_rates != NULL) {
/* limit frequencies */
if (limit_freq_to_174_4_khz)
sample_rates->rate.RATE_192 = 0;
if (limit_freq_to_96_khz) {
sample_rates->rate.RATE_192 = 0;
sample_rates->rate.RATE_176_4 = 0;
}
if (limit_freq_to_88_2_khz) {
sample_rates->rate.RATE_192 = 0;
sample_rates->rate.RATE_176_4 = 0;
sample_rates->rate.RATE_96 = 0;
}
if (limit_freq_to_48_khz) {
sample_rates->rate.RATE_192 = 0;
sample_rates->rate.RATE_176_4 = 0;
sample_rates->rate.RATE_96 = 0;
sample_rates->rate.RATE_88_2 = 0;
}
}
}
/*For DP SST, calculate if specified sample rates can fit into a given timing */
static void check_audio_bandwidth_dpsst(
const struct audio_crtc_info *crtc_info,
uint32_t channel_count,
union audio_sample_rates *sample_rates)
{
/* do nothing */
}
/*For DP MST, calculate if specified sample rates can fit into a given timing */
static void check_audio_bandwidth_dpmst(
const struct audio_crtc_info *crtc_info,
uint32_t channel_count,
union audio_sample_rates *sample_rates)
{
/* do nothing */
}
static void check_audio_bandwidth(
const struct audio_crtc_info *crtc_info,
uint32_t channel_count,
enum signal_type signal,
union audio_sample_rates *sample_rates)
{
switch (signal) {
case SIGNAL_TYPE_HDMI_TYPE_A:
check_audio_bandwidth_hdmi(
crtc_info, channel_count, sample_rates);
break;
case SIGNAL_TYPE_EDP:
case SIGNAL_TYPE_DISPLAY_PORT:
check_audio_bandwidth_dpsst(
crtc_info, channel_count, sample_rates);
break;
case SIGNAL_TYPE_DISPLAY_PORT_MST:
check_audio_bandwidth_dpmst(
crtc_info, channel_count, sample_rates);
break;
default:
break;
}
}
/* expose/not expose HBR capability to Audio driver */
static void set_high_bit_rate_capable(
struct audio *audio,
bool capable)
{
uint32_t value = 0;
/* set high bit rate audio capable*/
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR);
set_reg_field_value(value, capable,
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
HBR_CAPABLE);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value);
}
/* set video latency in in ms/2+1 */
static void set_video_latency(
struct audio *audio,
int latency_in_ms)
{
uint32_t value = 0;
if ((latency_in_ms < 0) || (latency_in_ms > 255))
return;
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
set_reg_field_value(value, latency_in_ms,
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
VIDEO_LIPSYNC);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
value);
}
/* set audio latency in in ms/2+1 */
static void set_audio_latency(
struct audio *audio,
int latency_in_ms)
{
uint32_t value = 0;
if (latency_in_ms < 0)
latency_in_ms = 0;
if (latency_in_ms > 255)
latency_in_ms = 255;
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
set_reg_field_value(value, latency_in_ms,
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
AUDIO_LIPSYNC);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
value);
}
void dce_aud_az_enable(struct audio *audio)
{
uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
if (get_reg_field_value(value,
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
AUDIO_ENABLED) != 1)
set_reg_field_value(value, 1,
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
AUDIO_ENABLED);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
}
void dce_aud_az_disable(struct audio *audio)
{
uint32_t value;
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
set_reg_field_value(value, 0,
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
AUDIO_ENABLED);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
}
void dce_aud_az_configure(
struct audio *audio,
enum signal_type signal,
const struct audio_crtc_info *crtc_info,
const struct audio_info *audio_info)
{
struct dce_audio *aud = DCE_AUD(audio);
uint32_t speakers = audio_info->flags.info.ALLSPEAKERS;
uint32_t value;
uint32_t field = 0;
enum audio_format_code audio_format_code;
uint32_t format_index;
uint32_t index;
bool is_ac3_supported = false;
union audio_sample_rates sample_rate;
uint32_t strlen = 0;
/* Speaker Allocation */
/*
uint32_t value;
uint32_t field = 0;*/
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
set_reg_field_value(value,
speakers,
AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
SPEAKER_ALLOCATION);
/* LFE_PLAYBACK_LEVEL = LFEPBL
* LFEPBL = 0 : Unknown or refer to other information
* LFEPBL = 1 : 0dB playback
* LFEPBL = 2 : +10dB playback
* LFE_BL = 3 : Reserved
*/
set_reg_field_value(value,
0,
AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
LFE_PLAYBACK_LEVEL);
/* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only.
* why are we writing to it? DCE8 does not write this */
set_reg_field_value(value,
0,
AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
HDMI_CONNECTION);
set_reg_field_value(value,
0,
AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
DP_CONNECTION);
field = get_reg_field_value(value,
AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
EXTRA_CONNECTION_INFO);
field &= ~0x1;
set_reg_field_value(value,
field,
AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
EXTRA_CONNECTION_INFO);
/* set audio for output signal */
switch (signal) {
case SIGNAL_TYPE_HDMI_TYPE_A:
set_reg_field_value(value,
1,
AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
HDMI_CONNECTION);
break;
case SIGNAL_TYPE_EDP:
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_DISPLAY_PORT_MST:
set_reg_field_value(value,
1,
AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
DP_CONNECTION);
break;
default:
BREAK_TO_DEBUGGER();
break;
}
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value);
/* Audio Descriptors */
/* pass through all formats */
for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT;
format_index++) {
audio_format_code =
(AUDIO_FORMAT_CODE_FIRST + format_index);
/* those are unsupported, skip programming */
if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO ||
audio_format_code == AUDIO_FORMAT_CODE_DST)
continue;
value = 0;
/* check if supported */
if (is_audio_format_supported(
audio_info, audio_format_code, &index)) {
const struct audio_mode *audio_mode =
&audio_info->modes[index];
union audio_sample_rates sample_rates =
audio_mode->sample_rates;
uint8_t byte2 = audio_mode->max_bit_rate;
/* adjust specific properties */
switch (audio_format_code) {
case AUDIO_FORMAT_CODE_LINEARPCM: {
check_audio_bandwidth(
crtc_info,
audio_mode->channel_count,
signal,
&sample_rates);
byte2 = audio_mode->sample_size;
set_reg_field_value(value,
sample_rates.all,
AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
SUPPORTED_FREQUENCIES_STEREO);
}
break;
case AUDIO_FORMAT_CODE_AC3:
is_ac3_supported = true;
break;
case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS:
case AUDIO_FORMAT_CODE_DTS_HD:
case AUDIO_FORMAT_CODE_MAT_MLP:
case AUDIO_FORMAT_CODE_DST:
case AUDIO_FORMAT_CODE_WMAPRO:
byte2 = audio_mode->vendor_specific;
break;
default:
break;
}
/* fill audio format data */
set_reg_field_value(value,
audio_mode->channel_count - 1,
AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
MAX_CHANNELS);
set_reg_field_value(value,
sample_rates.all,
AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
SUPPORTED_FREQUENCIES);
set_reg_field_value(value,
byte2,
AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
DESCRIPTOR_BYTE_2);
} /* if */
AZ_REG_WRITE(
AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index,
value);
} /* for */
if (is_ac3_supported)
/* todo: this reg global. why program global register? */
REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,
0x05);
/* check for 192khz/8-Ch support for HBR requirements */
sample_rate.all = 0;
sample_rate.rate.RATE_192 = 1;
check_audio_bandwidth(
crtc_info,
8,
signal,
&sample_rate);
set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192);
/* Audio and Video Lipsync */
set_video_latency(audio, audio_info->video_latency);
set_audio_latency(audio, audio_info->audio_latency);
value = 0;
set_reg_field_value(value, audio_info->manufacture_id,
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
MANUFACTURER_ID);
set_reg_field_value(value, audio_info->product_id,
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
PRODUCT_ID);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
value);
value = 0;
/*get display name string length */
while (audio_info->display_name[strlen++] != '\0') {
if (strlen >=
MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS)
break;
}
set_reg_field_value(value, strlen,
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
SINK_DESCRIPTION_LEN);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
value);
/*
*write the port ID:
*PORT_ID0 = display index
*PORT_ID1 = 16bit BDF
*(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function)
*/
value = 0;
set_reg_field_value(value, audio_info->port_id[0],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
PORT_ID0);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value);
value = 0;
set_reg_field_value(value, audio_info->port_id[1],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
PORT_ID1);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value);
/*write the 18 char monitor string */
value = 0;
set_reg_field_value(value, audio_info->display_name[0],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
DESCRIPTION0);
set_reg_field_value(value, audio_info->display_name[1],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
DESCRIPTION1);
set_reg_field_value(value, audio_info->display_name[2],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
DESCRIPTION2);
set_reg_field_value(value, audio_info->display_name[3],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
DESCRIPTION3);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value);
value = 0;
set_reg_field_value(value, audio_info->display_name[4],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
DESCRIPTION4);
set_reg_field_value(value, audio_info->display_name[5],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
DESCRIPTION5);
set_reg_field_value(value, audio_info->display_name[6],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
DESCRIPTION6);
set_reg_field_value(value, audio_info->display_name[7],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
DESCRIPTION7);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value);
value = 0;
set_reg_field_value(value, audio_info->display_name[8],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
DESCRIPTION8);
set_reg_field_value(value, audio_info->display_name[9],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
DESCRIPTION9);
set_reg_field_value(value, audio_info->display_name[10],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
DESCRIPTION10);
set_reg_field_value(value, audio_info->display_name[11],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
DESCRIPTION11);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value);
value = 0;
set_reg_field_value(value, audio_info->display_name[12],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
DESCRIPTION12);
set_reg_field_value(value, audio_info->display_name[13],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
DESCRIPTION13);
set_reg_field_value(value, audio_info->display_name[14],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
DESCRIPTION14);
set_reg_field_value(value, audio_info->display_name[15],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
DESCRIPTION15);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value);
value = 0;
set_reg_field_value(value, audio_info->display_name[16],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
DESCRIPTION16);
set_reg_field_value(value, audio_info->display_name[17],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
DESCRIPTION17);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value);
}
/*
* todo: wall clk related functionality probably belong to clock_src.
*/
/* search pixel clock value for Azalia HDMI Audio */
static bool get_azalia_clock_info_hdmi(
uint32_t crtc_pixel_clock_in_khz,
uint32_t actual_pixel_clock_in_khz,
struct azalia_clock_info *azalia_clock_info)
{
if (azalia_clock_info == NULL)
return false;
/* audio_dto_phase= 24 * 10,000;
* 24MHz in [100Hz] units */
azalia_clock_info->audio_dto_phase =
24 * 10000;
/* audio_dto_module = PCLKFrequency * 10,000;
* [khz] -> [100Hz] */
azalia_clock_info->audio_dto_module =
actual_pixel_clock_in_khz * 10;
return true;
}
static bool get_azalia_clock_info_dp(
uint32_t requested_pixel_clock_in_khz,
const struct audio_pll_info *pll_info,
struct azalia_clock_info *azalia_clock_info)
{
if (pll_info == NULL || azalia_clock_info == NULL)
return false;
/* Reported dpDtoSourceClockInkhz value for
* DCE8 already adjusted for SS, do not need any
* adjustment here anymore
*/
/*audio_dto_phase = 24 * 10,000;
* 24MHz in [100Hz] units */
azalia_clock_info->audio_dto_phase = 24 * 10000;
/*audio_dto_module = dpDtoSourceClockInkhz * 10,000;
* [khz] ->[100Hz] */
azalia_clock_info->audio_dto_module =
pll_info->dp_dto_source_clock_in_khz * 10;
return true;
}
void dce_aud_wall_dto_setup(
struct audio *audio,
enum signal_type signal,
const struct audio_crtc_info *crtc_info,
const struct audio_pll_info *pll_info)
{
struct dce_audio *aud = DCE_AUD(audio);
struct azalia_clock_info clock_info = { 0 };
if (dc_is_hdmi_signal(signal)) {
uint32_t src_sel;
/*DTO0 Programming goal:
-generate 24MHz, 128*Fs from 24MHz
-use DTO0 when an active HDMI port is connected
(optionally a DP is connected) */
/* calculate DTO settings */
get_azalia_clock_info_hdmi(
crtc_info->requested_pixel_clock,
crtc_info->calculated_pixel_clock,
&clock_info);
/* On TN/SI, Program DTO source select and DTO select before
programming DTO modulo and DTO phase. These bits must be
programmed first, otherwise there will be no HDMI audio at boot
up. This is a HW sequence change (different from old ASICs).
Caution when changing this programming sequence.
HDMI enabled, using DTO0
program master CRTC for DTO0 */
src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
DCCG_AUDIO_DTO_SEL, 0);
/* module */
REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
/* phase */
REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
} else {
/*DTO1 Programming goal:
-generate 24MHz, 512*Fs, 128*Fs from 24MHz
-default is to used DTO1, and switch to DTO0 when an audio
master HDMI port is connected
-use as default for DP
calculate DTO settings */
get_azalia_clock_info_dp(
crtc_info->requested_pixel_clock,
pll_info,
&clock_info);
/* Program DTO select before programming DTO modulo and DTO
phase. default to use DTO1 */
REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
DCCG_AUDIO_DTO_SEL, 1);
REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
DCCG_AUDIO_DTO_SEL, 1);
/* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
* Select 512fs for DP TODO: web register definition
* does not match register header file
* DCE11 version it's commented out while DCE8 it's set to 1
*/
/* module */
REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module);
/* phase */
REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
/* DAL2 code separate DCCG_AUDIO_DTO_SEL and
DCCG_AUDIO_DTO2_USE_512FBR_DTO programming into two different
location. merge together should not hurt */
/*value.bits.DCCG_AUDIO_DTO2_USE_512FBR_DTO = 1;
dal_write_reg(mmDCCG_AUDIO_DTO_SOURCE, value);*/
}
}
bool dce_aud_endpoint_valid(
struct audio *audio)
{
uint32_t value;
uint32_t port_connectivity;
value = AZ_REG_READ(
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
port_connectivity = get_reg_field_value(value,
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
PORT_CONNECTIVITY);
return !(port_connectivity == 1);
}
/* initialize HW state */
void dce_aud_hw_init(
struct audio *audio)
{
struct dce_audio *aud = DCE_AUD(audio);
/* we only need to program the following registers once, so we only do
it for the inst 0*/
if (audio->inst != 0)
return;
/* Suport R5 - 32khz
* Suport R6 - 44.1khz
* Suport R7 - 48khz
*/
REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
AUDIO_RATE_CAPABILITIES, 0x70);
/*Keep alive bit to verify HW block in BU. */
REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
CLKSTOP, 1,
EPSS, 1);
}
static const struct audio_funcs funcs = {
.endpoint_valid = dce_aud_endpoint_valid,
.hw_init = dce_aud_hw_init,
.wall_dto_setup = dce_aud_wall_dto_setup,
.az_enable = dce_aud_az_enable,
.az_disable = dce_aud_az_disable,
.az_configure = dce_aud_az_configure,
.destroy = dce_aud_destroy,
};
void dce_aud_destroy(struct audio **audio)
{
dm_free(*audio);
*audio = NULL;
}
struct audio *dce_audio_create(
struct dc_context *ctx,
unsigned int inst,
const struct dce_audio_registers *reg,
const struct dce_audio_shift *shifts,
const struct dce_aduio_mask *masks
)
{
struct dce_audio *audio = dm_alloc(sizeof(*audio));
if (audio == NULL) {
ASSERT_CRITICAL(audio);
return NULL;
}
audio->base.ctx = ctx;
audio->base.inst = inst;
audio->base.funcs = &funcs;
audio->regs = reg;
audio->shifts = shifts;
audio->masks = masks;
return &audio->base;
}

145
drivers/gpu/drm/amd/display/dc/dce/dce_audio.h Normal file
View File

@@ -0,0 +1,145 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_AUDIO_DCE_110_H__
#define __DAL_AUDIO_DCE_110_H__
#include "audio.h"
#define AUD_COMMON_REG_LIST(id)\
SRI(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZF0ENDPOINT, id),\
SRI(AZALIA_F0_CODEC_ENDPOINT_DATA, AZF0ENDPOINT, id),\
SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS),\
SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES),\
SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES),\
SR(DCCG_AUDIO_DTO_SOURCE),\
SR(DCCG_AUDIO_DTO0_MODULE),\
SR(DCCG_AUDIO_DTO0_PHASE),\
SR(DCCG_AUDIO_DTO1_MODULE),\
SR(DCCG_AUDIO_DTO1_PHASE)
/* set field name */
#define SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
#define AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)\
SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\
SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\
SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh)
#define AUD_COMMON_MASK_SH_LIST(mask_sh)\
AUD_COMMON_MASK_SH_LIST_BASE(mask_sh),\
SF(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
SF(AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh)
struct dce_audio_registers {
uint32_t AZALIA_F0_CODEC_ENDPOINT_INDEX;
uint32_t AZALIA_F0_CODEC_ENDPOINT_DATA;
uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS;
uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES;
uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES;
uint32_t DCCG_AUDIO_DTO_SOURCE;
uint32_t DCCG_AUDIO_DTO0_MODULE;
uint32_t DCCG_AUDIO_DTO0_PHASE;
uint32_t DCCG_AUDIO_DTO1_MODULE;
uint32_t DCCG_AUDIO_DTO1_PHASE;
uint32_t AUDIO_RATE_CAPABILITIES;
};
struct dce_audio_shift {
uint8_t AZALIA_ENDPOINT_REG_INDEX;
uint8_t AZALIA_ENDPOINT_REG_DATA;
uint8_t AUDIO_RATE_CAPABILITIES;
uint8_t CLKSTOP;
uint8_t EPSS;
uint8_t DCCG_AUDIO_DTO0_SOURCE_SEL;
uint8_t DCCG_AUDIO_DTO_SEL;
uint8_t DCCG_AUDIO_DTO0_MODULE;
uint8_t DCCG_AUDIO_DTO0_PHASE;
uint8_t DCCG_AUDIO_DTO1_MODULE;
uint8_t DCCG_AUDIO_DTO1_PHASE;
};
struct dce_aduio_mask {
uint32_t AZALIA_ENDPOINT_REG_INDEX;
uint32_t AZALIA_ENDPOINT_REG_DATA;
uint32_t AUDIO_RATE_CAPABILITIES;
uint32_t CLKSTOP;
uint32_t EPSS;
uint32_t DCCG_AUDIO_DTO0_SOURCE_SEL;
uint32_t DCCG_AUDIO_DTO_SEL;
uint32_t DCCG_AUDIO_DTO0_MODULE;
uint32_t DCCG_AUDIO_DTO0_PHASE;
uint32_t DCCG_AUDIO_DTO1_MODULE;
uint32_t DCCG_AUDIO_DTO1_PHASE;
};
struct dce_audio {
struct audio base;
const struct dce_audio_registers *regs;
const struct dce_audio_shift *shifts;
const struct dce_aduio_mask *masks;
};
struct audio *dce_audio_create(
struct dc_context *ctx,
unsigned int inst,
const struct dce_audio_registers *reg,
const struct dce_audio_shift *shifts,
const struct dce_aduio_mask *masks);
void dce_aud_destroy(struct audio **audio);
void dce_aud_hw_init(struct audio *audio);
void dce_aud_az_enable(struct audio *audio);
void dce_aud_az_disable(struct audio *audio);
void dce_aud_az_configure(struct audio *audio,
enum signal_type signal,
const struct audio_crtc_info *crtc_info,
const struct audio_info *audio_info);
void dce_aud_wall_dto_setup(struct audio *audio,
enum signal_type signal,
const struct audio_crtc_info *crtc_info,
const struct audio_pll_info *pll_info);
#endif /*__DAL_AUDIO_DCE_110_H__*/

1264
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c Normal file
View File

File diff suppressed because it is too large Load Diff

109
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h Normal file
View File

@@ -0,0 +1,109 @@
/* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_CLOCK_SOURCE_DCE_H__
#define __DC_CLOCK_SOURCE_DCE_H__
#include "../inc/clock_source.h"
#define TO_DCE110_CLK_SRC(clk_src)\
container_of(clk_src, struct dce110_clk_src, base)
#define CS_COMMON_REG_LIST_DCE_100_110(id) \
SRI(RESYNC_CNTL, PIXCLK, id), \
SRI(PLL_CNTL, BPHYC_PLL, id)
#define CS_COMMON_REG_LIST_DCE_80(id) \
SRI(RESYNC_CNTL, PIXCLK, id), \
SRI(PLL_CNTL, DCCG_PLL, id)
#define CS_COMMON_REG_LIST_DCE_112(id) \
SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id)
#define CS_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
#define CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\
CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\
CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\
CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh),\
#define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\
CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh),\
#define CS_REG_FIELD_LIST(type) \
type PLL_REF_DIV_SRC; \
type DCCG_DEEP_COLOR_CNTL1; \
type PHYPLLA_DCCG_DEEP_COLOR_CNTL; \
type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \
type PLL_POST_DIV_PIXCLK; \
type PLL_REF_DIV; \
struct dce110_clk_src_shift {
CS_REG_FIELD_LIST(uint8_t)
};
struct dce110_clk_src_mask{
CS_REG_FIELD_LIST(uint32_t)
};
struct dce110_clk_src_regs {
uint32_t RESYNC_CNTL;
uint32_t PIXCLK_RESYNC_CNTL;
uint32_t PLL_CNTL;
};
struct dce110_clk_src {
struct clock_source base;
const struct dce110_clk_src_regs *regs;
const struct dce110_clk_src_mask *cs_mask;
const struct dce110_clk_src_shift *cs_shift;
struct dc_bios *bios;
struct spread_spectrum_data *dp_ss_params;
uint32_t dp_ss_params_cnt;
struct spread_spectrum_data *hdmi_ss_params;
uint32_t hdmi_ss_params_cnt;
struct spread_spectrum_data *dvi_ss_params;
uint32_t dvi_ss_params_cnt;
uint32_t ext_clk_khz;
uint32_t ref_freq_khz;
struct calc_pll_clock_source calc_pll;
struct calc_pll_clock_source calc_pll_hdmi;
};
bool dce110_clk_src_construct(
struct dce110_clk_src *clk_src,
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id,
const struct dce110_clk_src_regs *regs,
const struct dce110_clk_src_shift *cs_shift,
const struct dce110_clk_src_mask *cs_mask);
#endif

195
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c Normal file
View File

@@ -0,0 +1,195 @@
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dce_hwseq.h"
#include "reg_helper.h"
#include "hw_sequencer.h"
#define CTX \
hws->ctx
#define REG(reg)\
hws->regs->reg
#undef FN
#define FN(reg_name, field_name) \
hws->shifts->field_name, hws->masks->field_name
void dce_enable_fe_clock(struct dce_hwseq *hws,
unsigned int fe_inst, bool enable)
{
REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst],
DCFE_CLOCK_ENABLE, enable);
}
void dce_pipe_control_lock(struct dce_hwseq *hws,
unsigned int blnd_inst,
enum pipe_lock_control control_mask,
bool lock)
{
uint32_t lock_val = lock ? 1 : 0;
uint32_t dcp_grph, scl, dcp_grph_surf, blnd, update_lock_mode;
uint32_t val = REG_GET_5(BLND_V_UPDATE_LOCK[blnd_inst],
BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph,
BLND_SCL_V_UPDATE_LOCK, &scl,
BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, &dcp_grph_surf,
BLND_BLND_V_UPDATE_LOCK, &blnd,
BLND_V_UPDATE_LOCK_MODE, &update_lock_mode);
if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
dcp_grph = lock_val;
if (control_mask & PIPE_LOCK_CONTROL_SCL)
scl = lock_val;
if (control_mask & PIPE_LOCK_CONTROL_SURFACE)
dcp_grph_surf = lock_val;
if (control_mask & PIPE_LOCK_CONTROL_BLENDER)
blnd = lock_val;
if (control_mask & PIPE_LOCK_CONTROL_MODE)
update_lock_mode = lock_val;
REG_SET_5(BLND_V_UPDATE_LOCK[blnd_inst], val,
BLND_DCP_GRPH_V_UPDATE_LOCK, dcp_grph,
BLND_SCL_V_UPDATE_LOCK, scl,
BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, dcp_grph_surf,
BLND_BLND_V_UPDATE_LOCK, blnd,
BLND_V_UPDATE_LOCK_MODE, update_lock_mode);
if (hws->wa.blnd_crtc_trigger)
if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER)) {
uint32_t value = REG_READ(CRTC_H_BLANK_START_END[blnd_inst]);
REG_WRITE(CRTC_H_BLANK_START_END[blnd_inst], value);
}
}
void dce_set_blender_mode(struct dce_hwseq *hws,
unsigned int blnd_inst,
enum blnd_mode mode)
{
uint32_t feedthrough = 1;
uint32_t blnd_mode = 0;
uint32_t multiplied_mode = 0;
uint32_t alpha_mode = 2;
switch (mode) {
case BLND_MODE_OTHER_PIPE:
feedthrough = 0;
blnd_mode = 1;
alpha_mode = 0;
break;
case BLND_MODE_BLENDING:
feedthrough = 0;
blnd_mode = 2;
alpha_mode = 0;
multiplied_mode = 1;
break;
case BLND_MODE_CURRENT_PIPE:
default:
if (REG(BLND_CONTROL[blnd_inst]) == REG(BLNDV_CONTROL) ||
blnd_inst == 0)
feedthrough = 0;
break;
}
REG_UPDATE_4(BLND_CONTROL[blnd_inst],
BLND_FEEDTHROUGH_EN, feedthrough,
BLND_ALPHA_MODE, alpha_mode,
BLND_MODE, blnd_mode,
BLND_MULTIPLIED_MODE, multiplied_mode);
}
static void dce_disable_sram_shut_down(struct dce_hwseq *hws)
{
if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL))
REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL,
DC_MEM_GLOBAL_PWR_REQ_DIS, 1);
}
static void dce_underlay_clock_enable(struct dce_hwseq *hws)
{
/* todo: why do we need this at boot? is dce_enable_fe_clock enough? */
if (REG(DCFEV_CLOCK_CONTROL))
REG_UPDATE(DCFEV_CLOCK_CONTROL,
DCFEV_CLOCK_ENABLE, 1);
}
static void enable_hw_base_light_sleep(void)
{
/* TODO: implement */
}
static void disable_sw_manual_control_light_sleep(void)
{
/* TODO: implement */
}
void dce_clock_gating_power_up(struct dce_hwseq *hws,
bool enable)
{
if (enable) {
enable_hw_base_light_sleep();
disable_sw_manual_control_light_sleep();
} else {
dce_disable_sram_shut_down(hws);
dce_underlay_clock_enable(hws);
}
}
void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
struct clock_source *clk_src,
unsigned int tg_inst)
{
if (clk_src->id == CLOCK_SOURCE_ID_DP_DTO) {
REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
DP_DTO0_ENABLE, 1);
} else if (clk_src->id >= CLOCK_SOURCE_COMBO_PHY_PLL0) {
uint32_t rate_source = clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0;
REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
PHYPLL_PIXEL_RATE_SOURCE, rate_source,
PIXEL_RATE_PLL_SOURCE, 0);
REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
DP_DTO0_ENABLE, 0);
} else if (clk_src->id <= CLOCK_SOURCE_ID_PLL2) {
uint32_t rate_source = clk_src->id - CLOCK_SOURCE_ID_PLL0;
REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst],
PIXEL_RATE_SOURCE, rate_source,
DP_DTO0_ENABLE, 0);
if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst]))
REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
PIXEL_RATE_PLL_SOURCE, 1);
} else {
DC_ERR("unknown clock source");
}
}

250
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h Normal file
View File

@@ -0,0 +1,250 @@
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DCE_HWSEQ_H__
#define __DCE_HWSEQ_H__
#include "hw_sequencer.h"
#define HWSEQ_DCEF_REG_LIST_DCE8() \
.DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \
.DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \
.DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \
.DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \
.DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \
.DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL
#define HWSEQ_DCEF_REG_LIST() \
SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
#define HWSEQ_BLND_REG_LIST() \
SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
SRII(BLND_V_UPDATE_LOCK, BLND, 1), \
SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
SRII(BLND_V_UPDATE_LOCK, BLND, 3), \
SRII(BLND_V_UPDATE_LOCK, BLND, 4), \
SRII(BLND_V_UPDATE_LOCK, BLND, 5), \
SRII(BLND_CONTROL, BLND, 0), \
SRII(BLND_CONTROL, BLND, 1), \
SRII(BLND_CONTROL, BLND, 2), \
SRII(BLND_CONTROL, BLND, 3), \
SRII(BLND_CONTROL, BLND, 4), \
SRII(BLND_CONTROL, BLND, 5)
#define HWSEQ_PIXEL_RATE_REG_LIST(blk) \
SRII(PIXEL_RATE_CNTL, blk, 0), \
SRII(PIXEL_RATE_CNTL, blk, 1), \
SRII(PIXEL_RATE_CNTL, blk, 2), \
SRII(PIXEL_RATE_CNTL, blk, 3), \
SRII(PIXEL_RATE_CNTL, blk, 4), \
SRII(PIXEL_RATE_CNTL, blk, 5)
#define HWSEQ_PHYPLL_REG_LIST(blk) \
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
#define HWSEQ_DCE11_REG_LIST_BASE() \
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
SR(DCFEV_CLOCK_CONTROL), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
SRII(BLND_V_UPDATE_LOCK, BLND, 0),\
SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
SRII(BLND_CONTROL, BLND, 0),\
SRII(BLND_CONTROL, BLND, 1),\
SR(BLNDV_CONTROL),\
HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
#define HWSEQ_DCE8_REG_LIST() \
HWSEQ_DCEF_REG_LIST_DCE8(), \
HWSEQ_BLND_REG_LIST(), \
HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
#define HWSEQ_DCE10_REG_LIST() \
HWSEQ_DCEF_REG_LIST(), \
HWSEQ_BLND_REG_LIST(), \
HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
#define HWSEQ_ST_REG_LIST() \
HWSEQ_DCE11_REG_LIST_BASE(), \
.DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \
.CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \
.BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \
.BLND_CONTROL[2] = mmBLNDV_CONTROL,
#define HWSEQ_CZ_REG_LIST() \
HWSEQ_DCE11_REG_LIST_BASE(), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
SRII(CRTC_H_BLANK_START_END, CRTC, 2), \
SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
SRII(BLND_CONTROL, BLND, 2), \
.DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \
.CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \
.BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \
.BLND_CONTROL[3] = mmBLNDV_CONTROL
#define HWSEQ_DCE112_REG_LIST() \
HWSEQ_DCE10_REG_LIST(), \
HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
HWSEQ_PHYPLL_REG_LIST(CRTC)
struct dce_hwseq_registers {
uint32_t DCFE_CLOCK_CONTROL[6];
uint32_t DCFEV_CLOCK_CONTROL;
uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL;
uint32_t BLND_V_UPDATE_LOCK[6];
uint32_t BLND_CONTROL[6];
uint32_t BLNDV_CONTROL;
uint32_t CRTC_H_BLANK_START_END[6];
uint32_t PIXEL_RATE_CNTL[6];
uint32_t PHYPLL_PIXEL_RATE_CNTL[6];
};
/* set field name */
#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
#define HWS_SF1(blk_name, reg_name, field_name, post_fix)\
.field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix
#define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\
HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\
SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
#define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\
HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\
HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\
HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\
HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\
HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\
HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh)
#define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\
HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\
HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
#define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\
HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\
HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)
#define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\
HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
#define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\
HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\
HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
#define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\
HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
#define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\
HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
#define HWSEQ_REG_FIED_LIST(type) \
type DCFE_CLOCK_ENABLE; \
type DCFEV_CLOCK_ENABLE; \
type DC_MEM_GLOBAL_PWR_REQ_DIS; \
type BLND_DCP_GRPH_V_UPDATE_LOCK; \
type BLND_SCL_V_UPDATE_LOCK; \
type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \
type BLND_BLND_V_UPDATE_LOCK; \
type BLND_V_UPDATE_LOCK_MODE; \
type BLND_FEEDTHROUGH_EN; \
type BLND_ALPHA_MODE; \
type BLND_MODE; \
type BLND_MULTIPLIED_MODE; \
type DP_DTO0_ENABLE; \
type PIXEL_RATE_SOURCE; \
type PHYPLL_PIXEL_RATE_SOURCE; \
type PIXEL_RATE_PLL_SOURCE; \
struct dce_hwseq_shift {
HWSEQ_REG_FIED_LIST(uint8_t)
};
struct dce_hwseq_mask {
HWSEQ_REG_FIED_LIST(uint32_t)
};
struct dce_hwseq_wa {
bool blnd_crtc_trigger;
};
struct dce_hwseq {
struct dc_context *ctx;
const struct dce_hwseq_registers *regs;
const struct dce_hwseq_shift *shifts;
const struct dce_hwseq_mask *masks;
struct dce_hwseq_wa wa;
};
enum blnd_mode {
BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
BLND_MODE_OTHER_PIPE, /* Data from other pipe only */
BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
};
void dce_enable_fe_clock(struct dce_hwseq *hwss,
unsigned int inst, bool enable);
void dce_pipe_control_lock(struct dce_hwseq *hws,
unsigned int blnd_inst,
enum pipe_lock_control control_mask,
bool lock);
void dce_set_blender_mode(struct dce_hwseq *hws,
unsigned int blnd_inst, enum blnd_mode mode);
void dce_clock_gating_power_up(struct dce_hwseq *hws,
bool enable);
void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
struct clock_source *clk_src,
unsigned int tg_inst);
#endif /*__DCE_HWSEQ_H__*/

2176
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c Normal file
View File

File diff suppressed because it is too large Load Diff

363
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h Normal file
View File

@@ -0,0 +1,363 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_LINK_ENCODER__DCE110_H__
#define __DC_LINK_ENCODER__DCE110_H__
#include "link_encoder.h"
#define TO_DCE110_LINK_ENC(link_encoder)\
container_of(link_encoder, struct dce110_link_encoder, base)
#define AUX_REG_LIST(id)\
SRI(AUX_CONTROL, DP_AUX, id), \
SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
#define HPD_REG_LIST(id)\
SRI(DC_HPD_CONTROL, HPD, id)
#define LE_COMMON_REG_LIST_BASE(id) \
SR(BL_PWM_CNTL), \
SR(BL_PWM_GRP1_REG_LOCK), \
SR(BL_PWM_PERIOD_CNTL), \
SR(LVTMA_PWRSEQ_CNTL), \
SR(LVTMA_PWRSEQ_STATE), \
SR(BL_PWM_CNTL2), \
SR(LVTMA_PWRSEQ_REF_DIV), \
SR(MASTER_COMM_DATA_REG1), \
SR(MASTER_COMM_DATA_REG2), \
SR(MASTER_COMM_DATA_REG3), \
SR(MASTER_COMM_CMD_REG), \
SR(MASTER_COMM_CNTL_REG), \
SR(DMCU_RAM_ACCESS_CTRL), \
SR(DMCU_IRAM_RD_CTRL), \
SR(DMCU_IRAM_RD_DATA), \
SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
SR(SMU_INTERRUPT_CONTROL), \
SRI(DIG_BE_CNTL, DIG, id), \
SRI(DIG_BE_EN_CNTL, DIG, id), \
SRI(DP_CONFIG, DP, id), \
SRI(DP_DPHY_CNTL, DP, id), \
SRI(DP_DPHY_PRBS_CNTL, DP, id), \
SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
SRI(DP_DPHY_SYM0, DP, id), \
SRI(DP_DPHY_SYM1, DP, id), \
SRI(DP_DPHY_SYM2, DP, id), \
SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
SRI(DP_LINK_CNTL, DP, id), \
SRI(DP_LINK_FRAMING_CNTL, DP, id), \
SRI(DP_MSE_SAT0, DP, id), \
SRI(DP_MSE_SAT1, DP, id), \
SRI(DP_MSE_SAT2, DP, id), \
SRI(DP_MSE_SAT_UPDATE, DP, id), \
SRI(DP_SEC_CNTL, DP, id), \
SRI(DP_VID_STREAM_CNTL, DP, id), \
SRI(DP_DPHY_FAST_TRAINING, DP, id), \
SRI(DP_SEC_CNTL1, DP, id)
#define LE_COMMON_REG_LIST(id)\
LE_COMMON_REG_LIST_BASE(id), \
SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
SR(BIOS_SCRATCH_2), \
SR(BL1_PWM_USER_LEVEL), \
SR(DCI_MEM_PWR_STATUS)
#define LE_DCE110_REG_LIST(id)\
LE_COMMON_REG_LIST_BASE(id), \
SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
SR(BIOS_SCRATCH_2), \
SR(BL1_PWM_USER_LEVEL), \
SR(DCI_MEM_PWR_STATUS)
#define LE_DCE80_REG_LIST(id)\
SR(BIOS_SCRATCH_2), \
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
SR(BL1_PWM_USER_LEVEL), \
LE_COMMON_REG_LIST_BASE(id)
struct dce110_link_enc_aux_registers {
uint32_t AUX_CONTROL;
uint32_t AUX_DPHY_RX_CONTROL0;
};
struct dce110_link_enc_hpd_registers {
uint32_t DC_HPD_CONTROL;
};
struct dce110_link_enc_registers {
/* BL registers */
uint32_t BL_PWM_CNTL;
uint32_t BL_PWM_GRP1_REG_LOCK;
uint32_t BL_PWM_PERIOD_CNTL;
uint32_t LVTMA_PWRSEQ_CNTL;
uint32_t LVTMA_PWRSEQ_STATE;
uint32_t BL_PWM_CNTL2;
uint32_t LVTMA_PWRSEQ_REF_DIV;
/* DMCU registers */
uint32_t BL1_PWM_USER_LEVEL;
uint32_t ABM0_BL1_PWM_USER_LEVEL;
uint32_t MASTER_COMM_DATA_REG1;
uint32_t MASTER_COMM_DATA_REG2;
uint32_t MASTER_COMM_DATA_REG3;
uint32_t MASTER_COMM_CMD_REG;
uint32_t MASTER_COMM_CNTL_REG;
uint32_t BIOS_SCRATCH_2;
uint32_t DMCU_RAM_ACCESS_CTRL;
uint32_t DCI_MEM_PWR_STATUS;
uint32_t DMU_MEM_PWR_CNTL;
uint32_t DMCU_IRAM_RD_CTRL;
uint32_t DMCU_IRAM_RD_DATA;
uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
uint32_t SMU_INTERRUPT_CONTROL;
/* Common DP registers */
uint32_t DIG_BE_CNTL;
uint32_t DIG_BE_EN_CNTL;
uint32_t DP_CONFIG;
uint32_t DP_DPHY_CNTL;
uint32_t DP_DPHY_INTERNAL_CTRL;
uint32_t DP_DPHY_PRBS_CNTL;
uint32_t DP_DPHY_SCRAM_CNTL;
uint32_t DP_DPHY_SYM0;
uint32_t DP_DPHY_SYM1;
uint32_t DP_DPHY_SYM2;
uint32_t DP_DPHY_TRAINING_PATTERN_SEL;
uint32_t DP_LINK_CNTL;
uint32_t DP_LINK_FRAMING_CNTL;
uint32_t DP_MSE_SAT0;
uint32_t DP_MSE_SAT1;
uint32_t DP_MSE_SAT2;
uint32_t DP_MSE_SAT_UPDATE;
uint32_t DP_SEC_CNTL;
uint32_t DP_VID_STREAM_CNTL;
uint32_t DP_DPHY_FAST_TRAINING;
uint32_t DP_DPHY_BS_SR_SWAP_CNTL;
uint32_t DP_SEC_CNTL1;
};
struct dce110_link_encoder {
struct link_encoder base;
const struct dce110_link_enc_registers *link_regs;
const struct dce110_link_enc_aux_registers *aux_regs;
const struct dce110_link_enc_hpd_registers *hpd_regs;
};
/*******************************************************************
* MASTER_COMM_DATA_REG1 Bit position Data
* 7:0 hyst_frames[7:0]
* 14:8 hyst_lines[6:0]
* 15 RFB_UPDATE_AUTO_EN
* 18:16 phy_num[2:0]
* 21:19 dcp_sel[2:0]
* 22 phy_type
* 23 frame_cap_ind
* 26:24 aux_chan[2:0]
* 30:27 aux_repeat[3:0]
* 31:31 reserved[31:31]
*******************************************************************/
union dce110_dmcu_psr_config_data_reg1 {
struct {
unsigned int timehyst_frames:8; /*[7:0]*/
unsigned int hyst_lines:7; /*[14:8]*/
unsigned int rfb_update_auto_en:1; /*[15:15]*/
unsigned int dp_port_num:3; /*[18:16]*/
unsigned int dcp_sel:3; /*[21:19]*/
unsigned int phy_type:1; /*[22:22]*/
unsigned int frame_cap_ind:1; /*[23:23]*/
unsigned int aux_chan:3; /*[26:24]*/
unsigned int aux_repeat:4; /*[30:27]*/
unsigned int reserved:1; /*[31:31]*/
} bits;
unsigned int u32All;
};
/*******************************************************************
* MASTER_COMM_DATA_REG2
*******************************************************************/
union dce110_dmcu_psr_config_data_reg2 {
struct {
unsigned int dig_fe:3; /*[2:0]*/
unsigned int dig_be:3; /*[5:3]*/
unsigned int skip_wait_for_pll_lock:1; /*[6:6]*/
unsigned int reserved:9; /*[15:7]*/
unsigned int frame_delay:8; /*[23:16]*/
unsigned int smu_phy_id:4; /*[27:24]*/
unsigned int num_of_controllers:4; /*[31:28]*/
} bits;
unsigned int u32All;
};
/*******************************************************************
* MASTER_COMM_DATA_REG3
*******************************************************************/
union dce110_dmcu_psr_config_data_reg3 {
struct {
unsigned int psr_level:16; /*[15:0]*/
unsigned int link_rate:4; /*[19:16]*/
unsigned int reserved:12; /*[31:20]*/
} bits;
unsigned int u32All;
};
struct dce110_abm_backlight_registers {
unsigned int vBL_PWM_CNTL;
unsigned int vBL_PWM_CNTL2;
unsigned int vBL_PWM_PERIOD_CNTL;
unsigned int vLVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV;
};
bool dce110_link_encoder_construct(
struct dce110_link_encoder *enc110,
const struct encoder_init_data *init_data,
const struct dce110_link_enc_registers *link_regs,
const struct dce110_link_enc_aux_registers *aux_regs,
const struct dce110_link_enc_hpd_registers *hpd_regs);
bool dce110_link_encoder_validate_dvi_output(
const struct dce110_link_encoder *enc110,
enum signal_type connector_signal,
enum signal_type signal,
const struct dc_crtc_timing *crtc_timing);
bool dce110_link_encoder_validate_rgb_output(
const struct dce110_link_encoder *enc110,
const struct dc_crtc_timing *crtc_timing);
bool dce110_link_encoder_validate_dp_output(
const struct dce110_link_encoder *enc110,
const struct dc_crtc_timing *crtc_timing);
bool dce110_link_encoder_validate_wireless_output(
const struct dce110_link_encoder *enc110,
const struct dc_crtc_timing *crtc_timing);
bool dce110_link_encoder_validate_output_with_stream(
struct link_encoder *enc,
struct pipe_ctx *pipe_ctx);
/****************** HW programming ************************/
/* initialize HW */ /* why do we initialze aux in here? */
void dce110_link_encoder_hw_init(struct link_encoder *enc);
void dce110_link_encoder_destroy(struct link_encoder **enc);
/* program DIG_MODE in DIG_BE */
/* TODO can this be combined with enable_output? */
void dce110_link_encoder_setup(
struct link_encoder *enc,
enum signal_type signal);
/* enables TMDS PHY output */
/* TODO: still need depth or just pass in adjusted pixel clock? */
void dce110_link_encoder_enable_tmds_output(
struct link_encoder *enc,
enum clock_source_id clock_source,
enum dc_color_depth color_depth,
bool hdmi,
bool dual_link,
uint32_t pixel_clock);
/* enables DP PHY output */
void dce110_link_encoder_enable_dp_output(
struct link_encoder *enc,
const struct dc_link_settings *link_settings,
enum clock_source_id clock_source);
/* enables DP PHY output in MST mode */
void dce110_link_encoder_enable_dp_mst_output(
struct link_encoder *enc,
const struct dc_link_settings *link_settings,
enum clock_source_id clock_source);
/* disable PHY output */
void dce110_link_encoder_disable_output(
struct link_encoder *link_enc,
enum signal_type signal);
/* set DP lane settings */
void dce110_link_encoder_dp_set_lane_settings(
struct link_encoder *enc,
const struct link_training_settings *link_settings);
void dce110_link_encoder_dp_set_phy_pattern(
struct link_encoder *enc,
const struct encoder_set_dp_phy_pattern_param *param);
/* programs DP MST VC payload allocation */
void dce110_link_encoder_update_mst_stream_allocation_table(
struct link_encoder *enc,
const struct link_mst_stream_allocation_table *table);
void dce110_link_encoder_set_lcd_backlight_level(
struct link_encoder *enc,
uint32_t level);
void dce110_link_encoder_set_dmcu_backlight_level(
struct link_encoder *enc,
uint32_t level,
uint32_t frame_ramp,
uint32_t controller_id);
void dce110_link_encoder_init_dmcu_backlight_settings(
struct link_encoder *enc);
void dce110_link_encoder_set_dmcu_abm_level(
struct link_encoder *enc,
uint32_t level);
void dce110_link_encoder_set_dmcu_psr_enable(
struct link_encoder *enc, bool enable);
void dce110_link_encoder_setup_dmcu_psr(struct link_encoder *enc,
struct psr_dmcu_context *psr_context);
void dce110_link_encoder_edp_backlight_control(
struct link_encoder *enc,
bool enable);
void dce110_link_encoder_edp_power_control(
struct link_encoder *enc,
bool power_up);
void dce110_link_encoder_connect_dig_be_to_fe(
struct link_encoder *enc,
enum engine_id engine,
bool connect);
void dce110_link_encoder_set_dp_phy_pattern_training_pattern(
struct link_encoder *enc,
uint32_t index);
void dce110_link_encoder_enable_hpd(struct link_encoder *enc);
void dce110_link_encoder_disable_hpd(struct link_encoder *enc);
#endif /* __DC_LINK_ENCODER__DCE110_H__ */

384
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c Normal file
View File

@@ -0,0 +1,384 @@
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "mem_input.h"
#include "reg_helper.h"
#define CTX \
mi->ctx
#define REG(reg)\
mi->regs->reg
#undef FN
#define FN(reg_name, field_name) \
mi->shifts->field_name, mi->masks->field_name
static void program_urgency_watermark(struct mem_input *mi,
uint32_t wm_select,
uint32_t urgency_low_wm,
uint32_t urgency_high_wm)
{
REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
URGENCY_WATERMARK_MASK, wm_select);
REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0,
URGENCY_LOW_WATERMARK, urgency_low_wm,
URGENCY_HIGH_WATERMARK, urgency_high_wm);
}
static void program_nbp_watermark(struct mem_input *mi,
uint32_t wm_select,
uint32_t nbp_wm)
{
if (REG(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL)) {
REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
NB_PSTATE_CHANGE_WATERMARK_MASK, wm_select);
REG_UPDATE_3(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
NB_PSTATE_CHANGE_ENABLE, 1,
NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, 1,
NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, 1);
REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
NB_PSTATE_CHANGE_WATERMARK, nbp_wm);
}
}
static void program_stutter_watermark(struct mem_input *mi,
uint32_t wm_select,
uint32_t stutter_mark)
{
REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, wm_select);
REG_UPDATE(DPG_PIPE_STUTTER_CONTROL,
STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark);
}
void dce_mem_input_program_display_marks(struct mem_input *mi,
struct bw_watermarks nbp,
struct bw_watermarks stutter,
struct bw_watermarks urgent,
uint32_t total_dest_line_time_ns)
{
uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
program_urgency_watermark(mi, 0, /* set a */
urgent.a_mark, total_dest_line_time_ns);
program_urgency_watermark(mi, 1, /* set b */
urgent.b_mark, total_dest_line_time_ns);
program_urgency_watermark(mi, 2, /* set c */
urgent.c_mark, total_dest_line_time_ns);
program_urgency_watermark(mi, 3, /* set d */
urgent.d_mark, total_dest_line_time_ns);
REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
STUTTER_ENABLE, stutter_en,
STUTTER_IGNORE_FBC, 1);
program_nbp_watermark(mi, 0, nbp.a_mark); /* set a */
program_nbp_watermark(mi, 1, nbp.b_mark); /* set b */
program_nbp_watermark(mi, 2, nbp.c_mark); /* set c */
program_nbp_watermark(mi, 3, nbp.d_mark); /* set d */
program_stutter_watermark(mi, 0, stutter.a_mark); /* set a */
program_stutter_watermark(mi, 1, stutter.b_mark); /* set b */
program_stutter_watermark(mi, 2, stutter.c_mark); /* set c */
program_stutter_watermark(mi, 3, stutter.d_mark); /* set d */
}
static void program_tiling(struct mem_input *mi,
const union dc_tiling_info *info)
{
if (mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */
REG_UPDATE_9(GRPH_CONTROL,
GRPH_NUM_BANKS, info->gfx8.num_banks,
GRPH_BANK_WIDTH, info->gfx8.bank_width,
GRPH_BANK_HEIGHT, info->gfx8.bank_height,
GRPH_MACRO_TILE_ASPECT, info->gfx8.tile_aspect,
GRPH_TILE_SPLIT, info->gfx8.tile_split,
GRPH_MICRO_TILE_MODE, info->gfx8.tile_mode,
GRPH_PIPE_CONFIG, info->gfx8.pipe_config,
GRPH_ARRAY_MODE, info->gfx8.array_mode,
GRPH_COLOR_EXPANSION_MODE, 1);
/* 01 - DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP: zero expansion for YCbCr */
/*
GRPH_Z, 0);
*/
}
}
static void program_size_and_rotation(
struct mem_input *mi,
enum dc_rotation_angle rotation,
const union plane_size *plane_size)
{
const struct rect *in_rect = &plane_size->grph.surface_size;
struct rect hw_rect = plane_size->grph.surface_size;
const uint32_t rotation_angles[ROTATION_ANGLE_COUNT] = {
[ROTATION_ANGLE_0] = 0,
[ROTATION_ANGLE_90] = 1,
[ROTATION_ANGLE_180] = 2,
[ROTATION_ANGLE_270] = 3,
};
if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) {
hw_rect.x = in_rect->y;
hw_rect.y = in_rect->x;
hw_rect.height = in_rect->width;
hw_rect.width = in_rect->height;
}
REG_SET(GRPH_X_START, 0,
GRPH_X_START, hw_rect.x);
REG_SET(GRPH_Y_START, 0,
GRPH_Y_START, hw_rect.y);
REG_SET(GRPH_X_END, 0,
GRPH_X_END, hw_rect.width);
REG_SET(GRPH_Y_END, 0,
GRPH_Y_END, hw_rect.height);
REG_SET(GRPH_PITCH, 0,
GRPH_PITCH, plane_size->grph.surface_pitch);
REG_SET(HW_ROTATION, 0,
GRPH_ROTATION_ANGLE, rotation_angles[rotation]);
}
static void program_grph_pixel_format(
struct mem_input *mi,
enum surface_pixel_format format)
{
uint32_t red_xbar = 0, blue_xbar = 0; /* no swap */
uint32_t grph_depth, grph_format;
uint32_t sign = 0, floating = 0;
if (format == SURFACE_PIXEL_FORMAT_GRPH_BGRA8888 ||
/*todo: doesn't look like we handle BGRA here,
* should problem swap endian*/
format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 ||
format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS ||
format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
/* ABGR formats */
red_xbar = 2;
blue_xbar = 2;
}
REG_SET_2(GRPH_SWAP_CNTL, 0,
GRPH_RED_CROSSBAR, red_xbar,
GRPH_BLUE_CROSSBAR, blue_xbar);
switch (format) {
case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
grph_depth = 0;
grph_format = 0;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
grph_depth = 1;
grph_format = 0;
break;
case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
grph_depth = 1;
grph_format = 1;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
grph_depth = 2;
grph_format = 0;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
grph_depth = 2;
grph_format = 1;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
sign = 1;
floating = 1;
/* no break */
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: /* shouldn't this get float too? */
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
grph_depth = 3;
grph_format = 0;
break;
default:
DC_ERR("unsupported grph pixel format");
break;
}
REG_UPDATE_2(GRPH_CONTROL,
GRPH_DEPTH, grph_depth,
GRPH_FORMAT, grph_format);
REG_UPDATE_4(PRESCALE_GRPH_CONTROL,
GRPH_PRESCALE_SELECT, floating,
GRPH_PRESCALE_R_SIGN, sign,
GRPH_PRESCALE_G_SIGN, sign,
GRPH_PRESCALE_B_SIGN, sign);
}
bool dce_mem_input_program_surface_config(struct mem_input *mi,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror)
{
REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1);
program_tiling(mi, tiling_info);
program_size_and_rotation(mi, rotation, plane_size);
if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &&
format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
program_grph_pixel_format(mi, format);
return true;
}
static uint32_t get_dmif_switch_time_us(
uint32_t h_total,
uint32_t v_total,
uint32_t pix_clk_khz)
{
uint32_t frame_time;
uint32_t pixels_per_second;
uint32_t pixels_per_frame;
uint32_t refresh_rate;
const uint32_t us_in_sec = 1000000;
const uint32_t min_single_frame_time_us = 30000;
/*return double of frame time*/
const uint32_t single_frame_time_multiplier = 2;
if (!h_total || v_total || !pix_clk_khz)
return single_frame_time_multiplier * min_single_frame_time_us;
/*TODO: should we use pixel format normalized pixel clock here?*/
pixels_per_second = pix_clk_khz * 1000;
pixels_per_frame = h_total * v_total;
if (!pixels_per_second || !pixels_per_frame) {
/* avoid division by zero */
ASSERT(pixels_per_frame);
ASSERT(pixels_per_second);
return single_frame_time_multiplier * min_single_frame_time_us;
}
refresh_rate = pixels_per_second / pixels_per_frame;
if (!refresh_rate) {
/* avoid division by zero*/
ASSERT(refresh_rate);
return single_frame_time_multiplier * min_single_frame_time_us;
}
frame_time = us_in_sec / refresh_rate;
if (frame_time < min_single_frame_time_us)
frame_time = min_single_frame_time_us;
frame_time *= single_frame_time_multiplier;
return frame_time;
}
void dce_mem_input_allocate_dmif(struct mem_input *mi,
uint32_t h_total,
uint32_t v_total,
uint32_t pix_clk_khz,
uint32_t total_stream_num)
{
const uint32_t retry_delay = 10;
uint32_t retry_count = get_dmif_switch_time_us(
h_total,
v_total,
pix_clk_khz) / retry_delay;
uint32_t pix_dur;
uint32_t buffers_allocated;
uint32_t dmif_buffer_control;
dmif_buffer_control = REG_GET(DMIF_BUFFER_CONTROL,
DMIF_BUFFERS_ALLOCATED, &buffers_allocated);
if (buffers_allocated == 2)
return;
REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control,
DMIF_BUFFERS_ALLOCATED, 2);
REG_WAIT(DMIF_BUFFER_CONTROL,
DMIF_BUFFERS_ALLOCATION_COMPLETED, 1,
retry_delay, retry_count);
if (pix_clk_khz != 0) {
pix_dur = 1000000000ULL / pix_clk_khz;
REG_UPDATE(DPG_PIPE_ARBITRATION_CONTROL1,
PIXEL_DURATION, pix_dur);
}
if (mi->wa.single_head_rdreq_dmif_limit) {
uint32_t eanble = (total_stream_num > 1) ? 0 :
mi->wa.single_head_rdreq_dmif_limit;
REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT,
ENABLE, eanble);
}
}
void dce_mem_input_free_dmif(struct mem_input *mi,
uint32_t total_stream_num)
{
uint32_t buffers_allocated;
uint32_t dmif_buffer_control;
dmif_buffer_control = REG_GET(DMIF_BUFFER_CONTROL,
DMIF_BUFFERS_ALLOCATED, &buffers_allocated);
if (buffers_allocated == 0)
return;
REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control,
DMIF_BUFFERS_ALLOCATED, 0);
REG_WAIT(DMIF_BUFFER_CONTROL,
DMIF_BUFFERS_ALLOCATION_COMPLETED, 1,
10, 0xBB8);
if (mi->wa.single_head_rdreq_dmif_limit) {
uint32_t eanble = (total_stream_num > 1) ? 0 :
mi->wa.single_head_rdreq_dmif_limit;
REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT,
ENABLE, eanble);
}
}

217
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h Normal file
View File

@@ -0,0 +1,217 @@
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DCE_MEM_INPUT_H__
#define __DCE_MEM_INPUT_H__
#define MI_DCE_BASE_REG_LIST(id)\
SRI(GRPH_ENABLE, DCP, id),\
SRI(GRPH_CONTROL, DCP, id),\
SRI(GRPH_X_START, DCP, id),\
SRI(GRPH_Y_START, DCP, id),\
SRI(GRPH_X_END, DCP, id),\
SRI(GRPH_Y_END, DCP, id),\
SRI(GRPH_PITCH, DCP, id),\
SRI(HW_ROTATION, DCP, id),\
SRI(GRPH_SWAP_CNTL, DCP, id),\
SRI(PRESCALE_GRPH_CONTROL, DCP, id),\
SRI(DPG_PIPE_ARBITRATION_CONTROL1, DMIF_PG, id),\
SRI(DPG_WATERMARK_MASK_CONTROL, DMIF_PG, id),\
SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\
SRI(DPG_PIPE_STUTTER_CONTROL, DMIF_PG, id),\
SRI(DMIF_BUFFER_CONTROL, PIPE, id)
#define MI_REG_LIST(id)\
MI_DCE_BASE_REG_LIST(id),\
SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id)
struct dce_mem_input_registers {
/* DCP */
uint32_t GRPH_ENABLE;
uint32_t GRPH_CONTROL;
uint32_t GRPH_X_START;
uint32_t GRPH_Y_START;
uint32_t GRPH_X_END;
uint32_t GRPH_Y_END;
uint32_t GRPH_PITCH;
uint32_t HW_ROTATION;
uint32_t GRPH_SWAP_CNTL;
uint32_t PRESCALE_GRPH_CONTROL;
/* DMIF_PG */
uint32_t DPG_PIPE_ARBITRATION_CONTROL1;
uint32_t DPG_WATERMARK_MASK_CONTROL;
uint32_t DPG_PIPE_URGENCY_CONTROL;
uint32_t DPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
uint32_t DPG_PIPE_LOW_POWER_CONTROL;
uint32_t DPG_PIPE_STUTTER_CONTROL;
uint32_t DPG_PIPE_STUTTER_CONTROL2;
/* DCI */
uint32_t DMIF_BUFFER_CONTROL;
/* MC_HUB */
uint32_t MC_HUB_RDREQ_DMIF_LIMIT;
};
/* Set_Filed_for_Block */
#define SFB(blk_name, reg_name, field_name, post_fix)\
.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
#define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk)\
SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh)
#define MI_DCP_MASK_SH_LIST(mask_sh, blk)\
SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\
SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\
SFB(blk, HW_ROTATION, GRPH_ROTATION_ANGLE, mask_sh),\
SFB(blk, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, mask_sh),\
SFB(blk, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, mask_sh),\
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh)
#define MI_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\
SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\
SFB(blk, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, mask_sh),\
SFB(blk, DPG_WATERMARK_MASK_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\
SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\
SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\
SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE, mask_sh),\
SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_IGNORE_FBC, mask_sh),\
SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
#define MI_DMIF_PG_MASK_SH_DCE(mask_sh, blk)\
SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\
SFB(blk, DPG_WATERMARK_MASK_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_ENABLE, mask_sh),\
SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\
SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh)
#define MI_DCE_MASK_SH_LIST(mask_sh)\
MI_DCP_MASK_SH_LIST(mask_sh,),\
MI_DMIF_PG_MASK_SH_LIST(mask_sh,),\
MI_DMIF_PG_MASK_SH_DCE(mask_sh,),\
MI_GFX8_TILE_MASK_SH_LIST(mask_sh,)
#define MI_REG_FIELD_LIST(type) \
type GRPH_ENABLE; \
type GRPH_X_START; \
type GRPH_Y_START; \
type GRPH_X_END; \
type GRPH_Y_END; \
type GRPH_PITCH; \
type GRPH_ROTATION_ANGLE; \
type GRPH_RED_CROSSBAR; \
type GRPH_BLUE_CROSSBAR; \
type GRPH_PRESCALE_SELECT; \
type GRPH_PRESCALE_R_SIGN; \
type GRPH_PRESCALE_G_SIGN; \
type GRPH_PRESCALE_B_SIGN; \
type GRPH_DEPTH; \
type GRPH_FORMAT; \
type GRPH_NUM_BANKS; \
type GRPH_BANK_WIDTH;\
type GRPH_BANK_HEIGHT;\
type GRPH_MACRO_TILE_ASPECT;\
type GRPH_TILE_SPLIT;\
type GRPH_MICRO_TILE_MODE;\
type GRPH_PIPE_CONFIG;\
type GRPH_ARRAY_MODE;\
type GRPH_COLOR_EXPANSION_MODE;\
type GRPH_SW_MODE; \
type GRPH_NUM_SHADER_ENGINES; \
type GRPH_NUM_PIPES; \
type PIXEL_DURATION; \
type URGENCY_WATERMARK_MASK; \
type PSTATE_CHANGE_WATERMARK_MASK; \
type NB_PSTATE_CHANGE_WATERMARK_MASK; \
type STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK; \
type URGENCY_LOW_WATERMARK; \
type URGENCY_HIGH_WATERMARK; \
type NB_PSTATE_CHANGE_ENABLE; \
type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST; \
type NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST; \
type NB_PSTATE_CHANGE_WATERMARK; \
type PSTATE_CHANGE_ENABLE; \
type PSTATE_CHANGE_URGENT_DURING_REQUEST; \
type PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST; \
type PSTATE_CHANGE_WATERMARK; \
type STUTTER_ENABLE; \
type STUTTER_IGNORE_FBC; \
type STUTTER_EXIT_SELF_REFRESH_WATERMARK; \
type DMIF_BUFFERS_ALLOCATED; \
type DMIF_BUFFERS_ALLOCATION_COMPLETED; \
type ENABLE; /* MC_HUB_RDREQ_DMIF_LIMIT */\
struct dce_mem_input_shift {
MI_REG_FIELD_LIST(uint8_t)
};
struct dce_mem_input_mask {
MI_REG_FIELD_LIST(uint32_t)
};
struct dce_mem_input_wa {
uint8_t single_head_rdreq_dmif_limit;
};
struct mem_input;
bool dce_mem_input_program_surface_config(struct mem_input *mi,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror);
void dce_mem_input_allocate_dmif(struct mem_input *mi,
uint32_t h_total,
uint32_t v_total,
uint32_t pix_clk_khz,
uint32_t total_stream_num);
void dce_mem_input_free_dmif(struct mem_input *mi,
uint32_t total_stream_num);
void dce_mem_input_program_display_marks(struct mem_input *mi,
struct bw_watermarks nbp,
struct bw_watermarks stutter,
struct bw_watermarks urgent,
uint32_t total_dest_line_time_ns);
#endif /*__DCE_MEM_INPUT_H__*/

501
drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c Normal file
View File

@@ -0,0 +1,501 @@
/*
* Copyright 2012-16 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "transform.h"
const uint16_t filter_2tap_16p[18] = {
4096, 0,
3840, 256,
3584, 512,
3328, 768,
3072, 1024,
2816, 1280,
2560, 1536,
2304, 1792,
2048, 2048
};
const uint16_t filter_3tap_16p_upscale[27] = {
2048, 2048, 0,
1708, 2424, 16348,
1372, 2796, 16308,
1056, 3148, 16272,
768, 3464, 16244,
512, 3728, 16236,
296, 3928, 16252,
124, 4052, 16296,
0, 4096, 0
};
const uint16_t filter_3tap_16p_117[27] = {
2048, 2048, 0,
1824, 2276, 16376,
1600, 2496, 16380,
1376, 2700, 16,
1156, 2880, 52,
948, 3032, 108,
756, 3144, 192,
580, 3212, 296,
428, 3236, 428
};
const uint16_t filter_3tap_16p_150[27] = {
2048, 2048, 0,
1872, 2184, 36,
1692, 2308, 88,
1516, 2420, 156,
1340, 2516, 236,
1168, 2592, 328,
1004, 2648, 440,
844, 2684, 560,
696, 2696, 696
};
const uint16_t filter_3tap_16p_183[27] = {
2048, 2048, 0,
1892, 2104, 92,
1744, 2152, 196,
1592, 2196, 300,
1448, 2232, 412,
1304, 2256, 528,
1168, 2276, 648,
1032, 2288, 772,
900, 2292, 900
};
const uint16_t filter_4tap_16p_upscale[36] = {
0, 4096, 0, 0,
16240, 4056, 180, 16380,
16136, 3952, 404, 16364,
16072, 3780, 664, 16344,
16040, 3556, 952, 16312,
16036, 3284, 1268, 16272,
16052, 2980, 1604, 16224,
16084, 2648, 1952, 16176,
16128, 2304, 2304, 16128
};
const uint16_t filter_4tap_16p_117[36] = {
428, 3236, 428, 0,
276, 3232, 604, 16364,
148, 3184, 800, 16340,
44, 3104, 1016, 16312,
16344, 2984, 1244, 16284,
16284, 2832, 1488, 16256,
16244, 2648, 1732, 16236,
16220, 2440, 1976, 16220,
16212, 2216, 2216, 16212
};
const uint16_t filter_4tap_16p_150[36] = {
696, 2700, 696, 0,
560, 2700, 848, 16364,
436, 2676, 1008, 16348,
328, 2628, 1180, 16336,
232, 2556, 1356, 16328,
152, 2460, 1536, 16328,
84, 2344, 1716, 16332,
28, 2208, 1888, 16348,
16376, 2052, 2052, 16376
};
const uint16_t filter_4tap_16p_183[36] = {
940, 2208, 940, 0,
832, 2200, 1052, 4,
728, 2180, 1164, 16,
628, 2148, 1280, 36,
536, 2100, 1392, 60,
448, 2044, 1504, 92,
368, 1976, 1612, 132,
296, 1900, 1716, 176,
232, 1812, 1812, 232
};
const uint16_t filter_2tap_64p[66] = {
4096, 0,
4032, 64,
3968, 128,
3904, 192,
3840, 256,
3776, 320,
3712, 384,
3648, 448,
3584, 512,
3520, 576,
3456, 640,
3392, 704,
3328, 768,
3264, 832,
3200, 896,
3136, 960,
3072, 1024,
3008, 1088,
2944, 1152,
2880, 1216,
2816, 1280,
2752, 1344,
2688, 1408,
2624, 1472,
2560, 1536,
2496, 1600,
2432, 1664,
2368, 1728,
2304, 1792,
2240, 1856,
2176, 1920,
2112, 1984,
2048, 2048 };
const uint16_t filter_3tap_64p_upscale[99] = {
2048, 2048, 0,
1960, 2140, 16376,
1876, 2236, 16364,
1792, 2328, 16356,
1708, 2424, 16348,
1620, 2516, 16336,
1540, 2612, 16328,
1456, 2704, 16316,
1372, 2796, 16308,
1292, 2884, 16296,
1212, 2976, 16288,
1136, 3060, 16280,
1056, 3148, 16272,
984, 3228, 16264,
908, 3312, 16256,
836, 3388, 16248,
768, 3464, 16244,
700, 3536, 16240,
636, 3604, 16236,
572, 3668, 16236,
512, 3728, 16236,
456, 3784, 16236,
400, 3836, 16240,
348, 3884, 16244,
296, 3928, 16252,
252, 3964, 16260,
204, 4000, 16268,
164, 4028, 16284,
124, 4052, 16296,
88, 4072, 16316,
56, 4084, 16336,
24, 4092, 16356,
0, 4096, 0
};
const uint16_t filter_3tap_64p_117[99] = {
2048, 2048, 0,
1992, 2104, 16380,
1936, 2160, 16380,
1880, 2220, 16376,
1824, 2276, 16376,
1768, 2332, 16376,
1712, 2388, 16376,
1656, 2444, 16376,
1600, 2496, 16380,
1544, 2548, 0,
1488, 2600, 4,
1432, 2652, 8,
1376, 2700, 16,
1320, 2748, 20,
1264, 2796, 32,
1212, 2840, 40,
1156, 2880, 52,
1104, 2920, 64,
1052, 2960, 80,
1000, 2996, 92,
948, 3032, 108,
900, 3060, 128,
852, 3092, 148,
804, 3120, 168,
756, 3144, 192,
712, 3164, 216,
668, 3184, 240,
624, 3200, 268,
580, 3212, 296,
540, 3220, 328,
500, 3228, 360,
464, 3232, 392,
428, 3236, 428
};
const uint16_t filter_3tap_64p_150[99] = {
2048, 2048, 0,
2004, 2080, 8,
1960, 2116, 16,
1916, 2148, 28,
1872, 2184, 36,
1824, 2216, 48,
1780, 2248, 60,
1736, 2280, 76,
1692, 2308, 88,
1648, 2336, 104,
1604, 2368, 120,
1560, 2392, 136,
1516, 2420, 156,
1472, 2444, 172,
1428, 2472, 192,
1384, 2492, 212,
1340, 2516, 236,
1296, 2536, 256,
1252, 2556, 280,
1212, 2576, 304,
1168, 2592, 328,
1124, 2608, 356,
1084, 2624, 384,
1044, 2636, 412,
1004, 2648, 440,
964, 2660, 468,
924, 2668, 500,
884, 2676, 528,
844, 2684, 560,
808, 2688, 596,
768, 2692, 628,
732, 2696, 664,
696, 2696, 696
};
const uint16_t filter_3tap_64p_183[99] = {
2048, 2048, 0,
2008, 2060, 20,
1968, 2076, 44,
1932, 2088, 68,
1892, 2104, 92,
1856, 2116, 120,
1816, 2128, 144,
1780, 2140, 168,
1744, 2152, 196,
1704, 2164, 220,
1668, 2176, 248,
1632, 2188, 272,
1592, 2196, 300,
1556, 2204, 328,
1520, 2216, 356,
1484, 2224, 384,
1448, 2232, 412,
1412, 2240, 440,
1376, 2244, 468,
1340, 2252, 496,
1304, 2256, 528,
1272, 2264, 556,
1236, 2268, 584,
1200, 2272, 616,
1168, 2276, 648,
1132, 2280, 676,
1100, 2284, 708,
1064, 2288, 740,
1032, 2288, 772,
996, 2292, 800,
964, 2292, 832,
932, 2292, 868,
900, 2292, 900
};
const uint16_t filter_4tap_64p_upscale[132] = {
0, 4096, 0, 0,
16344, 4092, 40, 0,
16308, 4084, 84, 16380,
16272, 4072, 132, 16380,
16240, 4056, 180, 16380,
16212, 4036, 232, 16376,
16184, 4012, 288, 16372,
16160, 3984, 344, 16368,
16136, 3952, 404, 16364,
16116, 3916, 464, 16360,
16100, 3872, 528, 16356,
16084, 3828, 596, 16348,
16072, 3780, 664, 16344,
16060, 3728, 732, 16336,
16052, 3676, 804, 16328,
16044, 3616, 876, 16320,
16040, 3556, 952, 16312,
16036, 3492, 1028, 16300,
16032, 3424, 1108, 16292,
16032, 3356, 1188, 16280,
16036, 3284, 1268, 16272,
16036, 3212, 1352, 16260,
16040, 3136, 1436, 16248,
16044, 3056, 1520, 16236,
16052, 2980, 1604, 16224,
16060, 2896, 1688, 16212,
16064, 2816, 1776, 16200,
16076, 2732, 1864, 16188,
16084, 2648, 1952, 16176,
16092, 2564, 2040, 16164,
16104, 2476, 2128, 16152,
16116, 2388, 2216, 16140,
16128, 2304, 2304, 16128 };
const uint16_t filter_4tap_64p_117[132] = {
420, 3248, 420, 0,
380, 3248, 464, 16380,
344, 3248, 508, 16372,
308, 3248, 552, 16368,
272, 3240, 596, 16364,
236, 3236, 644, 16356,
204, 3224, 692, 16352,
172, 3212, 744, 16344,
144, 3196, 796, 16340,
116, 3180, 848, 16332,
88, 3160, 900, 16324,
60, 3136, 956, 16320,
36, 3112, 1012, 16312,
16, 3084, 1068, 16304,
16380, 3056, 1124, 16296,
16360, 3024, 1184, 16292,
16340, 2992, 1244, 16284,
16324, 2956, 1304, 16276,
16308, 2920, 1364, 16268,
16292, 2880, 1424, 16264,
16280, 2836, 1484, 16256,
16268, 2792, 1548, 16252,
16256, 2748, 1608, 16244,
16248, 2700, 1668, 16240,
16240, 2652, 1732, 16232,
16232, 2604, 1792, 16228,
16228, 2552, 1856, 16224,
16220, 2500, 1916, 16220,
16216, 2444, 1980, 16216,
16216, 2388, 2040, 16216,
16212, 2332, 2100, 16212,
16212, 2276, 2160, 16212,
16212, 2220, 2220, 16212 };
const uint16_t filter_4tap_64p_150[132] = {
696, 2700, 696, 0,
660, 2704, 732, 16380,
628, 2704, 768, 16376,
596, 2704, 804, 16372,
564, 2700, 844, 16364,
532, 2696, 884, 16360,
500, 2692, 924, 16356,
472, 2684, 964, 16352,
440, 2676, 1004, 16352,
412, 2668, 1044, 16348,
384, 2656, 1088, 16344,
360, 2644, 1128, 16340,
332, 2632, 1172, 16336,
308, 2616, 1216, 16336,
284, 2600, 1260, 16332,
260, 2580, 1304, 16332,
236, 2560, 1348, 16328,
216, 2540, 1392, 16328,
196, 2516, 1436, 16328,
176, 2492, 1480, 16324,
156, 2468, 1524, 16324,
136, 2440, 1568, 16328,
120, 2412, 1612, 16328,
104, 2384, 1656, 16328,
88, 2352, 1700, 16332,
72, 2324, 1744, 16332,
60, 2288, 1788, 16336,
48, 2256, 1828, 16340,
36, 2220, 1872, 16344,
24, 2184, 1912, 16352,
12, 2148, 1952, 16356,
4, 2112, 1996, 16364,
16380, 2072, 2036, 16372 };
const uint16_t filter_4tap_64p_183[132] = {
944, 2204, 944, 0,
916, 2204, 972, 0,
888, 2200, 996, 0,
860, 2200, 1024, 4,
832, 2196, 1052, 4,
808, 2192, 1080, 8,
780, 2188, 1108, 12,
756, 2180, 1140, 12,
728, 2176, 1168, 16,
704, 2168, 1196, 20,
680, 2160, 1224, 24,
656, 2152, 1252, 28,
632, 2144, 1280, 36,
608, 2132, 1308, 40,
584, 2120, 1336, 48,
560, 2112, 1364, 52,
536, 2096, 1392, 60,
516, 2084, 1420, 68,
492, 2072, 1448, 76,
472, 2056, 1476, 84,
452, 2040, 1504, 92,
428, 2024, 1532, 100,
408, 2008, 1560, 112,
392, 1992, 1584, 120,
372, 1972, 1612, 132,
352, 1956, 1636, 144,
336, 1936, 1664, 156,
316, 1916, 1688, 168,
300, 1896, 1712, 180,
284, 1876, 1736, 192,
268, 1852, 1760, 208,
252, 1832, 1784, 220,
236, 1808, 1808, 236 };
const uint16_t *get_filter_3tap_16p(struct fixed31_32 ratio)
{
if (ratio.value < dal_fixed31_32_one.value)
return filter_3tap_16p_upscale;
else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
return filter_3tap_16p_117;
else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
return filter_3tap_16p_150;
else
return filter_3tap_16p_183;
}
const uint16_t *get_filter_3tap_64p(struct fixed31_32 ratio)
{
if (ratio.value < dal_fixed31_32_one.value)
return filter_3tap_64p_upscale;
else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
return filter_3tap_64p_117;
else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
return filter_3tap_64p_150;
else
return filter_3tap_64p_183;
}
const uint16_t *get_filter_4tap_16p(struct fixed31_32 ratio)
{
if (ratio.value < dal_fixed31_32_one.value)
return filter_4tap_16p_upscale;
else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
return filter_4tap_16p_117;
else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
return filter_4tap_16p_150;
else
return filter_4tap_16p_183;
}
const uint16_t *get_filter_4tap_64p(struct fixed31_32 ratio)
{
if (ratio.value < dal_fixed31_32_one.value)
return filter_4tap_64p_upscale;
else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
return filter_4tap_64p_117;
else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
return filter_4tap_64p_150;
else
return filter_4tap_64p_183;
}

1302
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c Normal file
View File

File diff suppressed because it is too large Load Diff

564
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h Normal file
View File

@@ -0,0 +1,564 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_STREAM_ENCODER_DCE110_H__
#define __DC_STREAM_ENCODER_DCE110_H__
#include "stream_encoder.h"
#define DCE110STRENC_FROM_STRENC(stream_encoder)\
container_of(stream_encoder, struct dce110_stream_encoder, base)
#ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
#define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L
#define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L
#define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004
#define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008
#endif
#define SE_COMMON_REG_LIST_DCE_BASE(id) \
SE_COMMON_REG_LIST_BASE(id),\
SRI(AFMT_AVI_INFO0, DIG, id), \
SRI(AFMT_AVI_INFO1, DIG, id), \
SRI(AFMT_AVI_INFO2, DIG, id), \
SRI(AFMT_AVI_INFO3, DIG, id)
#define SE_COMMON_REG_LIST_BASE(id) \
SRI(AFMT_GENERIC_0, DIG, id), \
SRI(AFMT_GENERIC_1, DIG, id), \
SRI(AFMT_GENERIC_2, DIG, id), \
SRI(AFMT_GENERIC_3, DIG, id), \
SRI(AFMT_GENERIC_4, DIG, id), \
SRI(AFMT_GENERIC_5, DIG, id), \
SRI(AFMT_GENERIC_6, DIG, id), \
SRI(AFMT_GENERIC_7, DIG, id), \
SRI(AFMT_GENERIC_HDR, DIG, id), \
SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
SRI(AFMT_60958_0, DIG, id), \
SRI(AFMT_60958_1, DIG, id), \
SRI(AFMT_60958_2, DIG, id), \
SRI(DIG_FE_CNTL, DIG, id), \
SRI(HDMI_CONTROL, DIG, id), \
SRI(HDMI_GC, DIG, id), \
SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
SRI(HDMI_ACR_32_0, DIG, id),\
SRI(HDMI_ACR_32_1, DIG, id),\
SRI(HDMI_ACR_44_0, DIG, id),\
SRI(HDMI_ACR_44_1, DIG, id),\
SRI(HDMI_ACR_48_0, DIG, id),\
SRI(HDMI_ACR_48_1, DIG, id),\
SRI(TMDS_CNTL, DIG, id), \
SRI(DP_MSE_RATE_CNTL, DP, id), \
SRI(DP_MSE_RATE_UPDATE, DP, id), \
SRI(DP_PIXEL_FORMAT, DP, id), \
SRI(DP_SEC_CNTL, DP, id), \
SRI(DP_STEER_FIFO, DP, id), \
SRI(DP_VID_M, DP, id), \
SRI(DP_VID_N, DP, id), \
SRI(DP_VID_STREAM_CNTL, DP, id), \
SRI(DP_VID_TIMING, DP, id), \
SRI(DP_SEC_AUD_N, DP, id), \
SRI(DP_SEC_TIMESTAMP, DP, id)
#define SE_COMMON_REG_LIST(id)\
SE_COMMON_REG_LIST_DCE_BASE(id), \
SRI(AFMT_CNTL, DIG, id)
#define SE_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
#define SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\
SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\
SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\
SE_SF(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
SE_SF(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
SE_SF(DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\
SE_SF(DP_PIXEL_FORMAT, DP_YCBCR_RANGE, mask_sh),\
SE_SF(HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
SE_SF(HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
SE_SF(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
SE_SF(HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
SE_SF(DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
SE_SF(DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
SE_SF(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
SE_SF(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\
SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\
SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\
SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\
SE_SF(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
SE_SF(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
SE_SF(DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
SE_SF(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
SE_SF(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
SE_SF(DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\
SE_SF(DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
SE_SF(DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
SE_SF(DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
SE_SF(DP_VID_N, DP_VID_N, mask_sh),\
SE_SF(DP_VID_M, DP_VID_M, mask_sh),\
SE_SF(DIG_FE_CNTL, DIG_START, mask_sh),\
SE_SF(AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
SE_SF(HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
SE_SF(HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
SE_SF(HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
SE_SF(HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
SE_SF(HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
SE_SF(HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
SE_SF(AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
SE_SF(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
SE_SF(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
SE_SF(DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
SE_SF(DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
SE_SF(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
SE_SF(DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
SE_SF(DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
SE_SF(DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh)
#define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\
SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)
#define SE_COMMON_MASK_SH_LIST_DCE80_100(mask_sh)\
SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
SE_SF(TMDS_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
SE_SF(TMDS_CNTL, TMDS_COLOR_FORMAT, mask_sh)
#define SE_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
SE_SF(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh)
#define SE_COMMON_MASK_SH_LIST_DCE112(mask_sh)\
SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
SE_SF(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
struct dce_stream_encoder_shift {
uint8_t AFMT_GENERIC_INDEX;
uint8_t AFMT_GENERIC0_UPDATE;
uint8_t AFMT_GENERIC2_UPDATE;
uint8_t AFMT_GENERIC_HB0;
uint8_t AFMT_GENERIC_HB1;
uint8_t AFMT_GENERIC_HB2;
uint8_t AFMT_GENERIC_HB3;
uint8_t AFMT_GENERIC_LOCK_STATUS;
uint8_t AFMT_GENERIC_CONFLICT;
uint8_t AFMT_GENERIC_CONFLICT_CLR;
uint8_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
uint8_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
uint8_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
uint8_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
uint8_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
uint8_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
uint8_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
uint8_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
uint8_t AFMT_GENERIC0_FRAME_UPDATE;
uint8_t AFMT_GENERIC1_FRAME_UPDATE;
uint8_t AFMT_GENERIC2_FRAME_UPDATE;
uint8_t AFMT_GENERIC3_FRAME_UPDATE;
uint8_t AFMT_GENERIC4_FRAME_UPDATE;
uint8_t AFMT_GENERIC5_FRAME_UPDATE;
uint8_t AFMT_GENERIC6_FRAME_UPDATE;
uint8_t AFMT_GENERIC7_FRAME_UPDATE;
uint8_t HDMI_GENERIC0_CONT;
uint8_t HDMI_GENERIC0_SEND;
uint8_t HDMI_GENERIC0_LINE;
uint8_t HDMI_GENERIC1_CONT;
uint8_t HDMI_GENERIC1_SEND;
uint8_t HDMI_GENERIC1_LINE;
uint8_t DP_PIXEL_ENCODING;
uint8_t DP_COMPONENT_DEPTH;
uint8_t DP_DYN_RANGE;
uint8_t DP_YCBCR_RANGE;
uint8_t HDMI_PACKET_GEN_VERSION;
uint8_t HDMI_KEEPOUT_MODE;
uint8_t HDMI_DEEP_COLOR_ENABLE;
uint8_t HDMI_CLOCK_CHANNEL_RATE;
uint8_t HDMI_DEEP_COLOR_DEPTH;
uint8_t HDMI_GC_CONT;
uint8_t HDMI_GC_SEND;
uint8_t HDMI_NULL_SEND;
uint8_t HDMI_DATA_SCRAMBLE_EN;
uint8_t HDMI_AUDIO_INFO_SEND;
uint8_t AFMT_AUDIO_INFO_UPDATE;
uint8_t HDMI_AUDIO_INFO_LINE;
uint8_t HDMI_GC_AVMUTE;
uint8_t DP_MSE_RATE_X;
uint8_t DP_MSE_RATE_Y;
uint8_t DP_MSE_RATE_UPDATE_PENDING;
uint8_t AFMT_AVI_INFO_VERSION;
uint8_t HDMI_AVI_INFO_SEND;
uint8_t HDMI_AVI_INFO_CONT;
uint8_t HDMI_AVI_INFO_LINE;
uint8_t DP_SEC_GSP0_ENABLE;
uint8_t DP_SEC_STREAM_ENABLE;
uint8_t DP_SEC_GSP1_ENABLE;
uint8_t DP_SEC_GSP2_ENABLE;
uint8_t DP_SEC_GSP3_ENABLE;
uint8_t DP_SEC_GSP4_ENABLE;
uint8_t DP_SEC_GSP5_ENABLE;
uint8_t DP_SEC_GSP6_ENABLE;
uint8_t DP_SEC_GSP7_ENABLE;
uint8_t DP_SEC_AVI_ENABLE;
uint8_t DP_SEC_MPG_ENABLE;
uint8_t DP_VID_STREAM_DIS_DEFER;
uint8_t DP_VID_STREAM_ENABLE;
uint8_t DP_VID_STREAM_STATUS;
uint8_t DP_STEER_FIFO_RESET;
uint8_t DP_VID_M_N_GEN_EN;
uint8_t DP_VID_N;
uint8_t DP_VID_M;
uint8_t DIG_START;
uint8_t AFMT_AUDIO_SRC_SELECT;
uint8_t AFMT_AUDIO_CHANNEL_ENABLE;
uint8_t HDMI_AUDIO_PACKETS_PER_LINE;
uint8_t HDMI_AUDIO_DELAY_EN;
uint8_t AFMT_60958_CS_UPDATE;
uint8_t AFMT_AUDIO_LAYOUT_OVRD;
uint8_t AFMT_60958_OSF_OVRD;
uint8_t HDMI_ACR_AUTO_SEND;
uint8_t HDMI_ACR_SOURCE;
uint8_t HDMI_ACR_AUDIO_PRIORITY;
uint8_t HDMI_ACR_CTS_32;
uint8_t HDMI_ACR_N_32;
uint8_t HDMI_ACR_CTS_44;
uint8_t HDMI_ACR_N_44;
uint8_t HDMI_ACR_CTS_48;
uint8_t HDMI_ACR_N_48;
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_L;
uint8_t AFMT_60958_CS_CLOCK_ACCURACY;
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_R;
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_2;
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_3;
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_4;
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_5;
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_6;
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_7;
uint8_t DP_SEC_AUD_N;
uint8_t DP_SEC_TIMESTAMP_MODE;
uint8_t DP_SEC_ASP_ENABLE;
uint8_t DP_SEC_ATP_ENABLE;
uint8_t DP_SEC_AIP_ENABLE;
uint8_t DP_SEC_ACM_ENABLE;
uint8_t AFMT_AUDIO_SAMPLE_SEND;
uint8_t AFMT_AUDIO_CLOCK_EN;
uint8_t TMDS_PIXEL_ENCODING;
uint8_t TMDS_COLOR_FORMAT;
uint8_t DP_DB_DISABLE;
uint8_t DP_MSA_MISC0;
uint8_t DP_MSA_HTOTAL;
uint8_t DP_MSA_VTOTAL;
uint8_t DP_MSA_HSTART;
uint8_t DP_MSA_VSTART;
uint8_t DP_MSA_HSYNCWIDTH;
uint8_t DP_MSA_HSYNCPOLARITY;
uint8_t DP_MSA_VSYNCWIDTH;
uint8_t DP_MSA_VSYNCPOLARITY;
uint8_t DP_MSA_HWIDTH;
uint8_t DP_MSA_VHEIGHT;
uint8_t HDMI_DB_DISABLE;
uint8_t DP_VID_N_MUL;
uint8_t DP_VID_M_DOUBLE_VALUE_EN;
};
struct dce_stream_encoder_mask {
uint32_t AFMT_GENERIC_INDEX;
uint32_t AFMT_GENERIC0_UPDATE;
uint32_t AFMT_GENERIC2_UPDATE;
uint32_t AFMT_GENERIC_HB0;
uint32_t AFMT_GENERIC_HB1;
uint32_t AFMT_GENERIC_HB2;
uint32_t AFMT_GENERIC_HB3;
uint32_t AFMT_GENERIC_LOCK_STATUS;
uint32_t AFMT_GENERIC_CONFLICT;
uint32_t AFMT_GENERIC_CONFLICT_CLR;
uint32_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
uint32_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
uint32_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
uint32_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
uint32_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
uint32_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
uint32_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
uint32_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
uint32_t AFMT_GENERIC0_FRAME_UPDATE;
uint32_t AFMT_GENERIC1_FRAME_UPDATE;
uint32_t AFMT_GENERIC2_FRAME_UPDATE;
uint32_t AFMT_GENERIC3_FRAME_UPDATE;
uint32_t AFMT_GENERIC4_FRAME_UPDATE;
uint32_t AFMT_GENERIC5_FRAME_UPDATE;
uint32_t AFMT_GENERIC6_FRAME_UPDATE;
uint32_t AFMT_GENERIC7_FRAME_UPDATE;
uint32_t HDMI_GENERIC0_CONT;
uint32_t HDMI_GENERIC0_SEND;
uint32_t HDMI_GENERIC0_LINE;
uint32_t HDMI_GENERIC1_CONT;
uint32_t HDMI_GENERIC1_SEND;
uint32_t HDMI_GENERIC1_LINE;
uint32_t DP_PIXEL_ENCODING;
uint32_t DP_COMPONENT_DEPTH;
uint32_t DP_DYN_RANGE;
uint32_t DP_YCBCR_RANGE;
uint32_t HDMI_PACKET_GEN_VERSION;
uint32_t HDMI_KEEPOUT_MODE;
uint32_t HDMI_DEEP_COLOR_ENABLE;
uint32_t HDMI_CLOCK_CHANNEL_RATE;
uint32_t HDMI_DEEP_COLOR_DEPTH;
uint32_t HDMI_GC_CONT;
uint32_t HDMI_GC_SEND;
uint32_t HDMI_NULL_SEND;
uint32_t HDMI_DATA_SCRAMBLE_EN;
uint32_t HDMI_AUDIO_INFO_SEND;
uint32_t AFMT_AUDIO_INFO_UPDATE;
uint32_t HDMI_AUDIO_INFO_LINE;
uint32_t HDMI_GC_AVMUTE;
uint32_t DP_MSE_RATE_X;
uint32_t DP_MSE_RATE_Y;
uint32_t DP_MSE_RATE_UPDATE_PENDING;
uint32_t AFMT_AVI_INFO_VERSION;
uint32_t HDMI_AVI_INFO_SEND;
uint32_t HDMI_AVI_INFO_CONT;
uint32_t HDMI_AVI_INFO_LINE;
uint32_t DP_SEC_GSP0_ENABLE;
uint32_t DP_SEC_STREAM_ENABLE;
uint32_t DP_SEC_GSP1_ENABLE;
uint32_t DP_SEC_GSP2_ENABLE;
uint32_t DP_SEC_GSP3_ENABLE;
uint32_t DP_SEC_GSP4_ENABLE;
uint32_t DP_SEC_GSP5_ENABLE;
uint32_t DP_SEC_GSP6_ENABLE;
uint32_t DP_SEC_GSP7_ENABLE;
uint32_t DP_SEC_AVI_ENABLE;
uint32_t DP_SEC_MPG_ENABLE;
uint32_t DP_VID_STREAM_DIS_DEFER;
uint32_t DP_VID_STREAM_ENABLE;
uint32_t DP_VID_STREAM_STATUS;
uint32_t DP_STEER_FIFO_RESET;
uint32_t DP_VID_M_N_GEN_EN;
uint32_t DP_VID_N;
uint32_t DP_VID_M;
uint32_t DIG_START;
uint32_t AFMT_AUDIO_SRC_SELECT;
uint32_t AFMT_AUDIO_CHANNEL_ENABLE;
uint32_t HDMI_AUDIO_PACKETS_PER_LINE;
uint32_t HDMI_AUDIO_DELAY_EN;
uint32_t AFMT_60958_CS_UPDATE;
uint32_t AFMT_AUDIO_LAYOUT_OVRD;
uint32_t AFMT_60958_OSF_OVRD;
uint32_t HDMI_ACR_AUTO_SEND;
uint32_t HDMI_ACR_SOURCE;
uint32_t HDMI_ACR_AUDIO_PRIORITY;
uint32_t HDMI_ACR_CTS_32;
uint32_t HDMI_ACR_N_32;
uint32_t HDMI_ACR_CTS_44;
uint32_t HDMI_ACR_N_44;
uint32_t HDMI_ACR_CTS_48;
uint32_t HDMI_ACR_N_48;
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_L;
uint32_t AFMT_60958_CS_CLOCK_ACCURACY;
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_R;
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_2;
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_3;
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_4;
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_5;
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_6;
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_7;
uint32_t DP_SEC_AUD_N;
uint32_t DP_SEC_TIMESTAMP_MODE;
uint32_t DP_SEC_ASP_ENABLE;
uint32_t DP_SEC_ATP_ENABLE;
uint32_t DP_SEC_AIP_ENABLE;
uint32_t DP_SEC_ACM_ENABLE;
uint32_t AFMT_AUDIO_SAMPLE_SEND;
uint32_t AFMT_AUDIO_CLOCK_EN;
uint32_t TMDS_PIXEL_ENCODING;
uint32_t TMDS_COLOR_FORMAT;
uint32_t DP_DB_DISABLE;
uint32_t DP_MSA_MISC0;
uint32_t DP_MSA_HTOTAL;
uint32_t DP_MSA_VTOTAL;
uint32_t DP_MSA_HSTART;
uint32_t DP_MSA_VSTART;
uint32_t DP_MSA_HSYNCWIDTH;
uint32_t DP_MSA_HSYNCPOLARITY;
uint32_t DP_MSA_VSYNCWIDTH;
uint32_t DP_MSA_VSYNCPOLARITY;
uint32_t DP_MSA_HWIDTH;
uint32_t DP_MSA_VHEIGHT;
uint32_t HDMI_DB_DISABLE;
uint32_t DP_VID_N_MUL;
uint32_t DP_VID_M_DOUBLE_VALUE_EN;
};
struct dce110_stream_enc_registers {
uint32_t AFMT_CNTL;
uint32_t AFMT_AVI_INFO0;
uint32_t AFMT_AVI_INFO1;
uint32_t AFMT_AVI_INFO2;
uint32_t AFMT_AVI_INFO3;
uint32_t AFMT_GENERIC_0;
uint32_t AFMT_GENERIC_1;
uint32_t AFMT_GENERIC_2;
uint32_t AFMT_GENERIC_3;
uint32_t AFMT_GENERIC_4;
uint32_t AFMT_GENERIC_5;
uint32_t AFMT_GENERIC_6;
uint32_t AFMT_GENERIC_7;
uint32_t AFMT_GENERIC_HDR;
uint32_t AFMT_INFOFRAME_CONTROL0;
uint32_t AFMT_VBI_PACKET_CONTROL;
uint32_t AFMT_VBI_PACKET_CONTROL1;
uint32_t AFMT_AUDIO_PACKET_CONTROL;
uint32_t AFMT_AUDIO_PACKET_CONTROL2;
uint32_t AFMT_AUDIO_SRC_CONTROL;
uint32_t AFMT_60958_0;
uint32_t AFMT_60958_1;
uint32_t AFMT_60958_2;
uint32_t DIG_FE_CNTL;
uint32_t DP_MSE_RATE_CNTL;
uint32_t DP_MSE_RATE_UPDATE;
uint32_t DP_PIXEL_FORMAT;
uint32_t DP_SEC_CNTL;
uint32_t DP_STEER_FIFO;
uint32_t DP_VID_M;
uint32_t DP_VID_N;
uint32_t DP_VID_STREAM_CNTL;
uint32_t DP_VID_TIMING;
uint32_t DP_SEC_AUD_N;
uint32_t DP_SEC_TIMESTAMP;
uint32_t HDMI_CONTROL;
uint32_t HDMI_GC;
uint32_t HDMI_GENERIC_PACKET_CONTROL0;
uint32_t HDMI_GENERIC_PACKET_CONTROL1;
uint32_t HDMI_GENERIC_PACKET_CONTROL2;
uint32_t HDMI_GENERIC_PACKET_CONTROL3;
uint32_t HDMI_INFOFRAME_CONTROL0;
uint32_t HDMI_INFOFRAME_CONTROL1;
uint32_t HDMI_VBI_PACKET_CONTROL;
uint32_t HDMI_AUDIO_PACKET_CONTROL;
uint32_t HDMI_ACR_PACKET_CONTROL;
uint32_t HDMI_ACR_32_0;
uint32_t HDMI_ACR_32_1;
uint32_t HDMI_ACR_44_0;
uint32_t HDMI_ACR_44_1;
uint32_t HDMI_ACR_48_0;
uint32_t HDMI_ACR_48_1;
uint32_t TMDS_CNTL;
};
struct dce110_stream_encoder {
struct stream_encoder base;
const struct dce110_stream_enc_registers *regs;
const struct dce_stream_encoder_shift *se_shift;
const struct dce_stream_encoder_mask *se_mask;
};
bool dce110_stream_encoder_construct(
struct dce110_stream_encoder *enc110,
struct dc_context *ctx,
struct dc_bios *bp,
enum engine_id eng_id,
const struct dce110_stream_enc_registers *regs,
const struct dce_stream_encoder_shift *se_shift,
const struct dce_stream_encoder_mask *se_mask);
void dce110_se_audio_mute_control(
struct stream_encoder *enc, bool mute);
void dce110_se_dp_audio_setup(
struct stream_encoder *enc,
unsigned int az_inst,
struct audio_info *info);
void dce110_se_dp_audio_enable(
struct stream_encoder *enc);
void dce110_se_dp_audio_disable(
struct stream_encoder *enc);
void dce110_se_hdmi_audio_setup(
struct stream_encoder *enc,
unsigned int az_inst,
struct audio_info *info,
struct audio_crtc_info *audio_crtc_info);
void dce110_se_hdmi_audio_disable(
struct stream_encoder *enc);
#endif /* __DC_STREAM_ENCODER_DCE110_H__ */

1002
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c Normal file
View File

File diff suppressed because it is too large Load Diff

313
drivers/gpu/drm/amd/display/dc/dce/dce_transform.h Normal file
View File

@@ -0,0 +1,313 @@
/*
* Copyright 2012-16 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef _DCE_DCE_TRANSFORM_H_
#define _DCE_DCE_TRANSFORM_H_
#include "transform.h"
#define TO_DCE_TRANSFORM(transform)\
container_of(transform, struct dce_transform, base)
#define LB_TOTAL_NUMBER_OF_ENTRIES 1712
#define LB_BITS_PER_ENTRY 144
#define XFM_COMMON_REG_LIST_DCE_BASE(id) \
SRI(LB_DATA_FORMAT, LB, id), \
SRI(GAMUT_REMAP_CONTROL, DCP, id), \
SRI(GAMUT_REMAP_C11_C12, DCP, id), \
SRI(GAMUT_REMAP_C13_C14, DCP, id), \
SRI(GAMUT_REMAP_C21_C22, DCP, id), \
SRI(GAMUT_REMAP_C23_C24, DCP, id), \
SRI(GAMUT_REMAP_C31_C32, DCP, id), \
SRI(GAMUT_REMAP_C33_C34, DCP, id), \
SRI(DENORM_CONTROL, DCP, id), \
SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \
SRI(OUT_ROUND_CONTROL, DCP, id), \
SRI(OUT_CLAMP_CONTROL_R_CR, DCP, id), \
SRI(OUT_CLAMP_CONTROL_G_Y, DCP, id), \
SRI(OUT_CLAMP_CONTROL_B_CB, DCP, id), \
SRI(SCL_MODE, SCL, id), \
SRI(SCL_TAP_CONTROL, SCL, id), \
SRI(SCL_CONTROL, SCL, id), \
SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
SRI(SCL_COEF_RAM_SELECT, SCL, id), \
SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \
SRI(VIEWPORT_START, SCL, id), \
SRI(VIEWPORT_SIZE, SCL, id), \
SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \
SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \
SRI(SCL_HORZ_FILTER_INIT, SCL, id), \
SRI(SCL_VERT_FILTER_INIT, SCL, id), \
SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \
SRI(LB_MEMORY_CTRL, LB, id), \
SRI(SCL_UPDATE, SCL, id)
#define XFM_COMMON_REG_LIST_DCE100(id) \
XFM_COMMON_REG_LIST_DCE_BASE(id), \
SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
SRI(DCFE_MEM_PWR_STATUS, CRTC, id)
#define XFM_COMMON_REG_LIST_DCE110(id) \
XFM_COMMON_REG_LIST_DCE_BASE(id), \
SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
SRI(DCFE_MEM_PWR_STATUS, DCFE, id)
#define XFM_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
#define XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \
XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \
XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \
XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \
XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \
XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \
XFM_SF(OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \
XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \
XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \
XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \
XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \
XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \
XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \
XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \
XFM_SF(LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \
XFM_SF(LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \
XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \
XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \
XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \
XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \
XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \
XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \
XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \
XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \
XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \
XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \
XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \
XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \
XFM_SF(GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \
XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \
XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
XFM_SF(SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \
XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \
XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \
XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \
XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \
XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \
XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \
XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \
XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \
XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \
XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \
XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \
XFM_SF(VIEWPORT_START, VIEWPORT_X_START, mask_sh), \
XFM_SF(VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \
XFM_SF(VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \
XFM_SF(VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \
XFM_SF(SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \
XFM_SF(SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \
XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \
XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \
XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \
XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \
XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \
XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \
XFM_SF(SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \
XFM_SF(SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \
XFM_SF(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \
XFM_SF(LB_DATA_FORMAT, ALPHA_EN, mask_sh)
#define XFM_COMMON_MASK_SH_LIST_DCE110(mask_sh) \
XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
XFM_SF(DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \
XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \
XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh)
#define XFM_REG_FIELD_LIST(type) \
type OUT_CLAMP_MIN_B_CB; \
type OUT_CLAMP_MAX_B_CB; \
type OUT_CLAMP_MIN_G_Y; \
type OUT_CLAMP_MAX_G_Y; \
type OUT_CLAMP_MIN_R_CR; \
type OUT_CLAMP_MAX_R_CR; \
type OUT_ROUND_TRUNC_MODE; \
type DCP_SPATIAL_DITHER_EN; \
type DCP_SPATIAL_DITHER_MODE; \
type DCP_SPATIAL_DITHER_DEPTH; \
type DCP_FRAME_RANDOM_ENABLE; \
type DCP_RGB_RANDOM_ENABLE; \
type DCP_HIGHPASS_RANDOM_ENABLE; \
type DENORM_MODE; \
type PIXEL_DEPTH; \
type PIXEL_EXPAN_MODE; \
type GAMUT_REMAP_C11; \
type GAMUT_REMAP_C12; \
type GAMUT_REMAP_C13; \
type GAMUT_REMAP_C14; \
type GAMUT_REMAP_C21; \
type GAMUT_REMAP_C22; \
type GAMUT_REMAP_C23; \
type GAMUT_REMAP_C24; \
type GAMUT_REMAP_C31; \
type GAMUT_REMAP_C32; \
type GAMUT_REMAP_C33; \
type GAMUT_REMAP_C34; \
type GRPH_GAMUT_REMAP_MODE; \
type SCL_MODE; \
type SCL_PSCL_EN; \
type SCL_H_NUM_OF_TAPS; \
type SCL_V_NUM_OF_TAPS; \
type SCL_BOUNDARY_MODE; \
type EXT_OVERSCAN_LEFT; \
type EXT_OVERSCAN_RIGHT; \
type EXT_OVERSCAN_TOP; \
type EXT_OVERSCAN_BOTTOM; \
type SCL_COEFF_MEM_PWR_DIS; \
type SCL_COEFF_MEM_PWR_STATE; \
type SCL_C_RAM_FILTER_TYPE; \
type SCL_C_RAM_PHASE; \
type SCL_C_RAM_TAP_PAIR_IDX; \
type SCL_C_RAM_EVEN_TAP_COEF_EN; \
type SCL_C_RAM_EVEN_TAP_COEF; \
type SCL_C_RAM_ODD_TAP_COEF_EN; \
type SCL_C_RAM_ODD_TAP_COEF; \
type VIEWPORT_X_START; \
type VIEWPORT_Y_START; \
type VIEWPORT_HEIGHT; \
type VIEWPORT_WIDTH; \
type SCL_H_SCALE_RATIO; \
type SCL_V_SCALE_RATIO; \
type SCL_H_INIT_INT; \
type SCL_H_INIT_FRAC; \
type SCL_V_INIT_INT; \
type SCL_V_INIT_FRAC; \
type LB_MEMORY_CONFIG; \
type LB_MEMORY_SIZE; \
type SCL_V_2TAP_HARDCODE_COEF_EN; \
type SCL_H_2TAP_HARDCODE_COEF_EN; \
type SCL_COEF_UPDATE_COMPLETE; \
type ALPHA_EN
struct dce_transform_shift {
XFM_REG_FIELD_LIST(uint8_t);
};
struct dce_transform_mask {
XFM_REG_FIELD_LIST(uint32_t);
};
struct dce_transform_registers {
uint32_t LB_DATA_FORMAT;
uint32_t GAMUT_REMAP_CONTROL;
uint32_t GAMUT_REMAP_C11_C12;
uint32_t GAMUT_REMAP_C13_C14;
uint32_t GAMUT_REMAP_C21_C22;
uint32_t GAMUT_REMAP_C23_C24;
uint32_t GAMUT_REMAP_C31_C32;
uint32_t GAMUT_REMAP_C33_C34;
uint32_t DENORM_CONTROL;
uint32_t DCP_SPATIAL_DITHER_CNTL;
uint32_t OUT_ROUND_CONTROL;
uint32_t OUT_CLAMP_CONTROL_R_CR;
uint32_t OUT_CLAMP_CONTROL_G_Y;
uint32_t OUT_CLAMP_CONTROL_B_CB;
uint32_t SCL_MODE;
uint32_t SCL_TAP_CONTROL;
uint32_t SCL_CONTROL;
uint32_t EXT_OVERSCAN_LEFT_RIGHT;
uint32_t EXT_OVERSCAN_TOP_BOTTOM;
uint32_t SCL_VERT_FILTER_CONTROL;
uint32_t SCL_HORZ_FILTER_CONTROL;
uint32_t DCFE_MEM_PWR_CTRL;
uint32_t DCFE_MEM_PWR_STATUS;
uint32_t SCL_COEF_RAM_SELECT;
uint32_t SCL_COEF_RAM_TAP_DATA;
uint32_t VIEWPORT_START;
uint32_t VIEWPORT_SIZE;
uint32_t SCL_HORZ_FILTER_SCALE_RATIO;
uint32_t SCL_VERT_FILTER_SCALE_RATIO;
uint32_t SCL_HORZ_FILTER_INIT;
uint32_t SCL_VERT_FILTER_INIT;
uint32_t SCL_AUTOMATIC_MODE_CONTROL;
uint32_t LB_MEMORY_CTRL;
uint32_t SCL_UPDATE;
};
struct init_int_and_frac {
uint32_t integer;
uint32_t fraction;
};
struct scl_ratios_inits {
uint32_t h_int_scale_ratio;
uint32_t v_int_scale_ratio;
struct init_int_and_frac h_init;
struct init_int_and_frac v_init;
};
enum ram_filter_type {
FILTER_TYPE_RGB_Y_VERTICAL = 0, /* 0 - RGB/Y Vertical filter */
FILTER_TYPE_CBCR_VERTICAL = 1, /* 1 - CbCr Vertical filter */
FILTER_TYPE_RGB_Y_HORIZONTAL = 2, /* 1 - RGB/Y Horizontal filter */
FILTER_TYPE_CBCR_HORIZONTAL = 3, /* 3 - CbCr Horizontal filter */
FILTER_TYPE_ALPHA_VERTICAL = 4, /* 4 - Alpha Vertical filter. */
FILTER_TYPE_ALPHA_HORIZONTAL = 5, /* 5 - Alpha Horizontal filter. */
};
struct dce_transform {
struct transform base;
const struct dce_transform_registers *regs;
const struct dce_transform_shift *xfm_shift;
const struct dce_transform_mask *xfm_mask;
const uint16_t *filter_v;
const uint16_t *filter_h;
const uint16_t *filter_v_c;
const uint16_t *filter_h_c;
int lb_pixel_depth_supported;
int lb_memory_size;
int lb_bits_per_entry;
bool prescaler_on;
};
bool dce_transform_construct(struct dce_transform *xfm110,
struct dc_context *ctx,
uint32_t inst,
const struct dce_transform_registers *regs,
const struct dce_transform_shift *xfm_shift,
const struct dce_transform_mask *xfm_mask);
bool dce_transform_get_optimal_number_of_taps(
struct transform *xfm,
struct scaler_data *scl_data,
const struct scaling_taps *in_taps);
#endif /* _DCE_DCE_TRANSFORM_H_ */