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drm/amd/dc: Add dc display driver (v2)
Supported DCE versions: 8.0, 10.0, 11.0, 11.2 v2: rebase against 4.11 Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland
committed by
Alex Deucher
Alex Deucher
parent
9c5b2b0d40
commit
4562236b3b
195
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
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195
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dce_hwseq.h"
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#include "reg_helper.h"
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#include "hw_sequencer.h"
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#define CTX \
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hws->ctx
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#define REG(reg)\
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hws->regs->reg
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#undef FN
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#define FN(reg_name, field_name) \
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hws->shifts->field_name, hws->masks->field_name
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void dce_enable_fe_clock(struct dce_hwseq *hws,
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unsigned int fe_inst, bool enable)
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{
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REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst],
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DCFE_CLOCK_ENABLE, enable);
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}
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void dce_pipe_control_lock(struct dce_hwseq *hws,
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unsigned int blnd_inst,
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enum pipe_lock_control control_mask,
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bool lock)
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{
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uint32_t lock_val = lock ? 1 : 0;
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uint32_t dcp_grph, scl, dcp_grph_surf, blnd, update_lock_mode;
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uint32_t val = REG_GET_5(BLND_V_UPDATE_LOCK[blnd_inst],
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BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph,
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BLND_SCL_V_UPDATE_LOCK, &scl,
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BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, &dcp_grph_surf,
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BLND_BLND_V_UPDATE_LOCK, &blnd,
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BLND_V_UPDATE_LOCK_MODE, &update_lock_mode);
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if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
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dcp_grph = lock_val;
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if (control_mask & PIPE_LOCK_CONTROL_SCL)
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scl = lock_val;
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if (control_mask & PIPE_LOCK_CONTROL_SURFACE)
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dcp_grph_surf = lock_val;
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if (control_mask & PIPE_LOCK_CONTROL_BLENDER)
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blnd = lock_val;
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if (control_mask & PIPE_LOCK_CONTROL_MODE)
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update_lock_mode = lock_val;
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REG_SET_5(BLND_V_UPDATE_LOCK[blnd_inst], val,
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BLND_DCP_GRPH_V_UPDATE_LOCK, dcp_grph,
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BLND_SCL_V_UPDATE_LOCK, scl,
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BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, dcp_grph_surf,
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BLND_BLND_V_UPDATE_LOCK, blnd,
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BLND_V_UPDATE_LOCK_MODE, update_lock_mode);
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if (hws->wa.blnd_crtc_trigger)
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if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER)) {
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uint32_t value = REG_READ(CRTC_H_BLANK_START_END[blnd_inst]);
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REG_WRITE(CRTC_H_BLANK_START_END[blnd_inst], value);
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}
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}
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void dce_set_blender_mode(struct dce_hwseq *hws,
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unsigned int blnd_inst,
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enum blnd_mode mode)
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{
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uint32_t feedthrough = 1;
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uint32_t blnd_mode = 0;
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uint32_t multiplied_mode = 0;
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uint32_t alpha_mode = 2;
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switch (mode) {
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case BLND_MODE_OTHER_PIPE:
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feedthrough = 0;
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blnd_mode = 1;
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alpha_mode = 0;
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break;
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case BLND_MODE_BLENDING:
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feedthrough = 0;
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blnd_mode = 2;
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alpha_mode = 0;
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multiplied_mode = 1;
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break;
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case BLND_MODE_CURRENT_PIPE:
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default:
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if (REG(BLND_CONTROL[blnd_inst]) == REG(BLNDV_CONTROL) ||
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blnd_inst == 0)
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feedthrough = 0;
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break;
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}
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REG_UPDATE_4(BLND_CONTROL[blnd_inst],
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BLND_FEEDTHROUGH_EN, feedthrough,
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BLND_ALPHA_MODE, alpha_mode,
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BLND_MODE, blnd_mode,
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BLND_MULTIPLIED_MODE, multiplied_mode);
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}
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static void dce_disable_sram_shut_down(struct dce_hwseq *hws)
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{
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if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL))
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REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL,
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DC_MEM_GLOBAL_PWR_REQ_DIS, 1);
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}
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static void dce_underlay_clock_enable(struct dce_hwseq *hws)
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{
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/* todo: why do we need this at boot? is dce_enable_fe_clock enough? */
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if (REG(DCFEV_CLOCK_CONTROL))
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REG_UPDATE(DCFEV_CLOCK_CONTROL,
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DCFEV_CLOCK_ENABLE, 1);
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}
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static void enable_hw_base_light_sleep(void)
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{
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/* TODO: implement */
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}
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static void disable_sw_manual_control_light_sleep(void)
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{
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/* TODO: implement */
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}
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void dce_clock_gating_power_up(struct dce_hwseq *hws,
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bool enable)
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{
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if (enable) {
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enable_hw_base_light_sleep();
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disable_sw_manual_control_light_sleep();
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} else {
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dce_disable_sram_shut_down(hws);
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dce_underlay_clock_enable(hws);
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}
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}
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void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
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struct clock_source *clk_src,
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unsigned int tg_inst)
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{
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if (clk_src->id == CLOCK_SOURCE_ID_DP_DTO) {
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REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
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DP_DTO0_ENABLE, 1);
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} else if (clk_src->id >= CLOCK_SOURCE_COMBO_PHY_PLL0) {
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uint32_t rate_source = clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0;
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REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
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PHYPLL_PIXEL_RATE_SOURCE, rate_source,
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PIXEL_RATE_PLL_SOURCE, 0);
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REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
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DP_DTO0_ENABLE, 0);
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} else if (clk_src->id <= CLOCK_SOURCE_ID_PLL2) {
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uint32_t rate_source = clk_src->id - CLOCK_SOURCE_ID_PLL0;
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REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst],
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PIXEL_RATE_SOURCE, rate_source,
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DP_DTO0_ENABLE, 0);
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if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst]))
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REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
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PIXEL_RATE_PLL_SOURCE, 1);
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} else {
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DC_ERR("unknown clock source");
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}
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}
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