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drm/amd/dc: Add dc display driver (v2)

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Supported DCE versions: 8.0, 10.0, 11.0, 11.2

v2: rebase against 4.11

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland
2017-09-12 15:58:20 -04:00
committed by Alex Deucher
parent 9c5b2b0d40
commit 4562236b3b
315 changed files with 99491 additions and 37 deletions
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55
drivers/gpu/drm/amd/display/include/asic_capability_interface.h Normal file
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of enc software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and enc permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_ASIC_CAPABILITY_INTERFACE_H__
#define __DAL_ASIC_CAPABILITY_INTERFACE_H__
/* Include */
#include "include/asic_capability_types.h"
/* Forward declaration */
struct hw_asic_id;
/* ASIC capability */
struct asic_capability {
struct dc_context *ctx;
struct asic_caps caps;
struct asic_stereo_3d_caps stereo_3d_caps;
struct asic_bugs bugs;
uint32_t data[ASIC_DATA_MAX_NUMBER];
};
/**
* Interfaces
*/
/* Create and initialize ASIC capability */
struct asic_capability *dal_asic_capability_create(struct hw_asic_id *init,
struct dc_context *ctx);
/* Destroy ASIC capability and free memory space */
void dal_asic_capability_destroy(struct asic_capability **cap);
#endif /* __DAL_ASIC_CAPABILITY_INTERFACE_H__ */

116
drivers/gpu/drm/amd/display/include/asic_capability_types.h Normal file
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_ASIC_CAPABILITY_TYPES_H__
#define __DAL_ASIC_CAPABILITY_TYPES_H__
/*
* ASIC Capabilities
*/
struct asic_caps {
bool CONSUMER_SINGLE_SELECTED_TIMING:1;
bool UNDERSCAN_ADJUST:1;
bool DELTA_SIGMA_SUPPORT:1;
bool PANEL_SELF_REFRESH_SUPPORTED:1;
bool IS_FUSION:1;
bool DP_MST_SUPPORTED:1;
bool UNDERSCAN_FOR_HDMI_ONLY:1;
bool DVI_CLOCK_SHARE_CAPABILITY:1;
bool SUPPORT_CEA861E_FINAL:1;
bool MIRABILIS_SUPPORTED:1;
bool MIRABILIS_ENABLED_BY_DEFAULT:1;
bool DEVICE_TAG_REMAP_SUPPORTED:1;
bool HEADLESS_NO_OPM_SUPPORTED:1;
bool WIRELESS_LIMIT_TO_720P:1;
bool WIRELESS_FULL_TIMING_ADJUSTMENT:1;
bool WIRELESS_TIMING_ADJUSTMENT:1;
bool WIRELESS_COMPRESSED_AUDIO:1;
bool VCE_SUPPORTED:1;
bool HPD_CHECK_FOR_EDID:1;
bool NEED_MC_TUNING:1;
bool SKIP_PSR_WAIT_FOR_PLL_LOCK_BIT:1;
bool DFSBYPASS_DYNAMIC_SUPPORT:1;
bool SUPPORT_8BPP:1;
};
/*
* ASIC Stereo 3D Caps
*/
struct asic_stereo_3d_caps {
bool SUPPORTED:1;
bool DISPLAY_BASED_ON_WS:1;
bool HDMI_FRAME_PACK:1;
bool INTERLACE_FRAME_PACK:1;
bool DISPLAYPORT_FRAME_PACK:1;
bool DISPLAYPORT_FRAME_ALT:1;
bool INTERLEAVE:1;
};
/*
* ASIC Bugs
*/
struct asic_bugs {
bool MST_SYMBOL_MISALIGNMENT:1;
bool PSR_2X_LANE_GANGING:1;
bool LB_WA_IS_SUPPORTED:1;
bool ROM_REGISTER_ACCESS:1;
bool PSR_WA_OVERSCAN_CRC_ERROR:1;
};
/*
* ASIC Data
*/
enum asic_data {
ASIC_DATA_FIRST = 0,
ASIC_DATA_DCE_VERSION = ASIC_DATA_FIRST,
ASIC_DATA_DCE_VERSION_MINOR,
ASIC_DATA_LINEBUFFER_SIZE,
ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY,
ASIC_DATA_MC_LATENCY,
ASIC_DATA_MC_LATENCY_SLOW,
ASIC_DATA_MEMORYTYPE_MULTIPLIER,
ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR,
ASIC_DATA_MAX_UNDERSCAN_PERCENTAGE,
ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY,
ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN,
ASIC_DATA_DOWNSCALE_LIMIT,
ASIC_DATA_MAX_NUMBER /* end of enum */
};
/*
* ASIC Feature Flags
*/
struct asic_feature_flags {
union {
uint32_t raw;
struct {
uint32_t LEGACY_CLIENT:1;
uint32_t PACKED_PIXEL_FORMAT:1;
uint32_t WORKSTATION_STEREO:1;
uint32_t WORKSTATION:1;
} bits;
};
};
#endif /* __DAL_ASIC_CAPABILITY_TYPES_H__ */

106
drivers/gpu/drm/amd/display/include/audio_types.h Normal file
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __AUDIO_TYPES_H__
#define __AUDIO_TYPES_H__
#include "signal_types.h"
#define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
#define MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 18
#define MULTI_CHANNEL_SPLIT_NO_ASSO_INFO 0xFFFFFFFF
struct audio_crtc_info {
uint32_t h_total;
uint32_t h_active;
uint32_t v_active;
uint32_t pixel_repetition;
uint32_t requested_pixel_clock; /* in KHz */
uint32_t calculated_pixel_clock; /* in KHz */
uint32_t refresh_rate;
enum dc_color_depth color_depth;
bool interlaced;
};
struct azalia_clock_info {
uint32_t pixel_clock_in_10khz;
uint32_t audio_dto_phase;
uint32_t audio_dto_module;
uint32_t audio_dto_wall_clock_ratio;
};
enum audio_dto_source {
DTO_SOURCE_UNKNOWN = 0,
DTO_SOURCE_ID0,
DTO_SOURCE_ID1,
DTO_SOURCE_ID2,
DTO_SOURCE_ID3,
DTO_SOURCE_ID4,
DTO_SOURCE_ID5
};
/* PLL information required for AZALIA DTO calculation */
struct audio_pll_info {
uint32_t dp_dto_source_clock_in_khz;
uint32_t feed_back_divider;
enum audio_dto_source dto_source;
bool ss_enabled;
uint32_t ss_percentage;
uint32_t ss_percentage_divider;
};
struct audio_channel_associate_info {
union {
struct {
uint32_t ALL_CHANNEL_FL:4;
uint32_t ALL_CHANNEL_FR:4;
uint32_t ALL_CHANNEL_FC:4;
uint32_t ALL_CHANNEL_Sub:4;
uint32_t ALL_CHANNEL_SL:4;
uint32_t ALL_CHANNEL_SR:4;
uint32_t ALL_CHANNEL_BL:4;
uint32_t ALL_CHANNEL_BR:4;
} bits;
uint32_t u32all;
};
};
struct audio_output {
/* Front DIG id. */
enum engine_id engine_id;
/* encoder output signal */
enum signal_type signal;
/* video timing */
struct audio_crtc_info crtc_info;
/* PLL for audio */
struct audio_pll_info pll_info;
};
enum audio_payload {
CHANNEL_SPLIT_MAPPINGCHANG = 0x9,
};
#endif /* __AUDIO_TYPES_H__ */

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drivers/gpu/drm/amd/display/include/bios_parser_interface.h Normal file
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_BIOS_PARSER_INTERFACE_H__
#define __DAL_BIOS_PARSER_INTERFACE_H__
#include "dc_bios_types.h"
struct bios_parser;
struct bp_init_data {
struct dc_context *ctx;
uint8_t *bios;
};
struct dc_bios *dal_bios_parser_create(
struct bp_init_data *init,
enum dce_version dce_version);
void dal_bios_parser_destroy(struct dc_bios **dcb);
#endif /* __DAL_BIOS_PARSER_INTERFACE_H__ */

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drivers/gpu/drm/amd/display/include/bios_parser_types.h Normal file
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_BIOS_PARSER_TYPES_H__
#define __DAL_BIOS_PARSER_TYPES_H__
#include "dm_services.h"
#include "include/signal_types.h"
#include "include/grph_object_ctrl_defs.h"
#include "include/gpio_types.h"
#include "include/link_service_types.h"
/* TODO: include signal_types.h and remove this enum */
enum as_signal_type {
AS_SIGNAL_TYPE_NONE = 0L, /* no signal */
AS_SIGNAL_TYPE_DVI,
AS_SIGNAL_TYPE_HDMI,
AS_SIGNAL_TYPE_LVDS,
AS_SIGNAL_TYPE_DISPLAY_PORT,
AS_SIGNAL_TYPE_GPU_PLL,
AS_SIGNAL_TYPE_UNKNOWN
};
enum bp_result {
BP_RESULT_OK = 0, /* There was no error */
BP_RESULT_BADINPUT, /*Bad input parameter */
BP_RESULT_BADBIOSTABLE, /* Bad BIOS table */
BP_RESULT_UNSUPPORTED, /* BIOS Table is not supported */
BP_RESULT_NORECORD, /* Record can't be found */
BP_RESULT_FAILURE
};
enum bp_encoder_control_action {
/* direct VBIOS translation! Just to simplify the translation */
ENCODER_CONTROL_DISABLE = 0,
ENCODER_CONTROL_ENABLE,
ENCODER_CONTROL_SETUP,
ENCODER_CONTROL_INIT
};
enum bp_transmitter_control_action {
/* direct VBIOS translation! Just to simplify the translation */
TRANSMITTER_CONTROL_DISABLE = 0,
TRANSMITTER_CONTROL_ENABLE,
TRANSMITTER_CONTROL_BACKLIGHT_OFF,
TRANSMITTER_CONTROL_BACKLIGHT_ON,
TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS,
TRANSMITTER_CONTROL_LCD_SETF_TEST_START,
TRANSMITTER_CONTROL_LCD_SELF_TEST_STOP,
TRANSMITTER_CONTROL_INIT,
TRANSMITTER_CONTROL_DEACTIVATE,
TRANSMITTER_CONTROL_ACTIAVATE,
TRANSMITTER_CONTROL_SETUP,
TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS,
/* ATOM_TRANSMITTER_ACTION_POWER_ON. This action is for eDP only
* (power up the panel)
*/
TRANSMITTER_CONTROL_POWER_ON,
/* ATOM_TRANSMITTER_ACTION_POWER_OFF. This action is for eDP only
* (power down the panel)
*/
TRANSMITTER_CONTROL_POWER_OFF
};
enum bp_external_encoder_control_action {
EXTERNAL_ENCODER_CONTROL_DISABLE = 0,
EXTERNAL_ENCODER_CONTROL_ENABLE = 1,
EXTERNAL_ENCODER_CONTROL_INIT = 0x7,
EXTERNAL_ENCODER_CONTROL_SETUP = 0xf,
EXTERNAL_ENCODER_CONTROL_UNBLANK = 0x10,
EXTERNAL_ENCODER_CONTROL_BLANK = 0x11,
};
enum bp_pipe_control_action {
ASIC_PIPE_DISABLE = 0,
ASIC_PIPE_ENABLE,
ASIC_PIPE_INIT
};
struct bp_encoder_control {
enum bp_encoder_control_action action;
enum engine_id engine_id;
enum transmitter transmitter;
enum signal_type signal;
enum dc_lane_count lanes_number;
enum dc_color_depth color_depth;
bool enable_dp_audio;
uint32_t pixel_clock; /* khz */
};
struct bp_external_encoder_control {
enum bp_external_encoder_control_action action;
enum engine_id engine_id;
enum dc_link_rate link_rate;
enum dc_lane_count lanes_number;
enum signal_type signal;
enum dc_color_depth color_depth;
bool coherent;
struct graphics_object_id encoder_id;
struct graphics_object_id connector_obj_id;
uint32_t pixel_clock; /* in KHz */
};
struct bp_crtc_source_select {
enum engine_id engine_id;
enum controller_id controller_id;
/* from GPU Tx aka asic_signal */
enum signal_type signal;
/* sink_signal may differ from asicSignal if Translator encoder */
enum signal_type sink_signal;
enum display_output_bit_depth display_output_bit_depth;
bool enable_dp_audio;
};
struct bp_transmitter_control {
enum bp_transmitter_control_action action;
enum engine_id engine_id;
enum transmitter transmitter; /* PhyId */
enum dc_lane_count lanes_number;
enum clock_source_id pll_id; /* needed for DCE 4.0 */
enum signal_type signal;
enum dc_color_depth color_depth; /* not used for DCE6.0 */
enum hpd_source_id hpd_sel; /* ucHPDSel, used for DCe6.0 */
struct graphics_object_id connector_obj_id;
/* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should
* be pixel clock * deep_color_ratio (in KHz)
*/
uint32_t pixel_clock;
uint32_t lane_select;
uint32_t lane_settings;
bool coherent;
bool multi_path;
bool single_pll_mode;
};
struct bp_blank_crtc_parameters {
enum controller_id controller_id;
uint32_t black_color_rcr;
uint32_t black_color_gy;
uint32_t black_color_bcb;
};
struct bp_hw_crtc_timing_parameters {
enum controller_id controller_id;
/* horizontal part */
uint32_t h_total;
uint32_t h_addressable;
uint32_t h_overscan_left;
uint32_t h_overscan_right;
uint32_t h_sync_start;
uint32_t h_sync_width;
/* vertical part */
uint32_t v_total;
uint32_t v_addressable;
uint32_t v_overscan_top;
uint32_t v_overscan_bottom;
uint32_t v_sync_start;
uint32_t v_sync_width;
struct timing_flags {
uint32_t INTERLACE:1;
uint32_t PIXEL_REPETITION:4;
uint32_t HSYNC_POSITIVE_POLARITY:1;
uint32_t VSYNC_POSITIVE_POLARITY:1;
uint32_t HORZ_COUNT_BY_TWO:1;
} flags;
};
struct bp_hw_crtc_overscan_parameters {
enum controller_id controller_id;
uint32_t h_overscan_left;
uint32_t h_overscan_right;
uint32_t v_overscan_top;
uint32_t v_overscan_bottom;
};
struct bp_adjust_pixel_clock_parameters {
/* Input: Signal Type - to be converted to Encoder mode */
enum signal_type signal_type;
/* Input: Encoder object id */
struct graphics_object_id encoder_object_id;
/* Input: Pixel Clock (requested Pixel clock based on Video timing
* standard used) in KHz
*/
uint32_t pixel_clock;
/* Output: Adjusted Pixel Clock (after VBIOS exec table) in KHz */
uint32_t adjusted_pixel_clock;
/* Output: If non-zero, this refDiv value should be used to calculate
* other ppll params */
uint32_t reference_divider;
/* Output: If non-zero, this postDiv value should be used to calculate
* other ppll params */
uint32_t pixel_clock_post_divider;
/* Input: Enable spread spectrum */
bool ss_enable;
};
struct bp_pixel_clock_parameters {
enum controller_id controller_id; /* (Which CRTC uses this PLL) */
enum clock_source_id pll_id; /* Clock Source Id */
/* signal_type -> Encoder Mode - needed by VBIOS Exec table */
enum signal_type signal_type;
/* Adjusted Pixel Clock (after VBIOS exec table)
* that becomes Target Pixel Clock (KHz) */
uint32_t target_pixel_clock;
/* Calculated Reference divider of Display PLL */
uint32_t reference_divider;
/* Calculated Feedback divider of Display PLL */
uint32_t feedback_divider;
/* Calculated Fractional Feedback divider of Display PLL */
uint32_t fractional_feedback_divider;
/* Calculated Pixel Clock Post divider of Display PLL */
uint32_t pixel_clock_post_divider;
struct graphics_object_id encoder_object_id; /* Encoder object id */
/* VBIOS returns a fixed display clock when DFS-bypass feature
* is enabled (KHz) */
uint32_t dfs_bypass_display_clock;
/* color depth to support HDMI deep color */
enum transmitter_color_depth color_depth;
struct program_pixel_clock_flags {
uint32_t FORCE_PROGRAMMING_OF_PLL:1;
/* Use Engine Clock as source for Display Clock when
* programming PLL */
uint32_t USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK:1;
/* Use external reference clock (refDivSrc for PLL) */
uint32_t SET_EXTERNAL_REF_DIV_SRC:1;
/* Force program PHY PLL only */
uint32_t PROGRAM_PHY_PLL_ONLY:1;
/* Support for YUV420 */
uint32_t SUPPORT_YUV_420:1;
/* Use XTALIN reference clock source */
uint32_t SET_XTALIN_REF_SRC:1;
/* Use GENLK reference clock source */
uint32_t SET_GENLOCK_REF_DIV_SRC:1;
} flags;
};
struct bp_display_clock_parameters {
uint32_t target_display_clock; /* KHz */
/* Actual Display Clock set due to clock divider granularity KHz */
uint32_t actual_display_clock;
/* Actual Post Divider ID used to generate the actual clock */
uint32_t actual_post_divider_id;
};
enum bp_dce_clock_type {
DCECLOCK_TYPE_DISPLAY_CLOCK = 0,
DCECLOCK_TYPE_DPREFCLK = 1
};
/* DCE Clock Parameters structure for SetDceClock Exec command table */
struct bp_set_dce_clock_parameters {
enum clock_source_id pll_id; /* Clock Source Id */
/* Display clock or DPREFCLK value */
uint32_t target_clock_frequency;
/* Clock to set: =0: DISPCLK =1: DPREFCLK =2: PIXCLK */
enum bp_dce_clock_type clock_type;
struct set_dce_clock_flags {
uint32_t USE_GENERICA_AS_SOURCE_FOR_DPREFCLK:1;
/* Use XTALIN reference clock source */
uint32_t USE_XTALIN_AS_SOURCE_FOR_DPREFCLK:1;
/* Use PCIE reference clock source */
uint32_t USE_PCIE_AS_SOURCE_FOR_DPREFCLK:1;
/* Use GENLK reference clock source */
uint32_t USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK:1;
} flags;
};
struct spread_spectrum_flags {
/* 1 = Center Spread; 0 = down spread */
uint32_t CENTER_SPREAD:1;
/* 1 = external; 0 = internal */
uint32_t EXTERNAL_SS:1;
/* 1 = delta-sigma type parameter; 0 = ver1 */
uint32_t DS_TYPE:1;
};
struct bp_spread_spectrum_parameters {
enum clock_source_id pll_id;
uint32_t percentage;
uint32_t ds_frac_amount;
union {
struct {
uint32_t step;
uint32_t delay;
uint32_t range; /* In Hz unit */
} ver1;
struct {
uint32_t feedback_amount;
uint32_t nfrac_amount;
uint32_t ds_frac_size;
} ds;
};
struct spread_spectrum_flags flags;
};
struct bp_encoder_cap_info {
uint32_t DP_HBR2_CAP:1;
uint32_t DP_HBR2_EN:1;
uint32_t DP_HBR3_EN:1;
uint32_t HDMI_6GB_EN:1;
uint32_t RESERVED:30;
};
struct bp_gpio_cntl_info {
uint32_t id;
enum gpio_pin_output_state state;
};
#endif /*__DAL_BIOS_PARSER_TYPES_H__ */

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drivers/gpu/drm/amd/display/include/dal_asic_id.h Normal file
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_ASIC_ID_H__
#define __DAL_ASIC_ID_H__
/*
* ASIC internal revision ID
*/
/* DCE80 (based on ci_id.h in Perforce) */
#define CI_BONAIRE_M_A0 0x14
#define CI_BONAIRE_M_A1 0x15
#define CI_HAWAII_P_A0 0x28
#define CI_UNKNOWN 0xFF
#define ASIC_REV_IS_BONAIRE_M(rev) \
((rev >= CI_BONAIRE_M_A0) && (rev < CI_HAWAII_P_A0))
#define ASIC_REV_IS_HAWAII_P(rev) \
(rev >= CI_HAWAII_P_A0)
/* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */
#define KV_SPECTRE_A0 0x01
/* KV2 with Spooky GFX core, including downgraded from Spectre core,
* 3-4-1-1 (CU-Pix-Primitive-RB) */
#define KV_SPOOKY_A0 0x41
/* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
#define KB_KALINDI_A0 0x81
/* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
#define KB_KALINDI_A1 0x82
/* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
#define BV_KALINDI_A2 0x85
/* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
#define ML_GODAVARI_A0 0xA1
/* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
#define ML_GODAVARI_A1 0xA2
#define KV_UNKNOWN 0xFF
#define ASIC_REV_IS_KALINDI(rev) \
((rev >= KB_KALINDI_A0) && (rev < KV_UNKNOWN))
#define ASIC_REV_IS_BHAVANI(rev) \
((rev >= BV_KALINDI_A2) && (rev < ML_GODAVARI_A0))
#define ASIC_REV_IS_GODAVARI(rev) \
((rev >= ML_GODAVARI_A0) && (rev < KV_UNKNOWN))
/* VI Family */
/* DCE10 */
#define VI_TONGA_P_A0 20
#define VI_TONGA_P_A1 21
#define VI_FIJI_P_A0 60
/* DCE112 */
#define VI_POLARIS10_P_A0 80
#define VI_POLARIS11_M_A0 90
#define VI_UNKNOWN 0xFF
#define ASIC_REV_IS_TONGA_P(eChipRev) ((eChipRev >= VI_TONGA_P_A0) && \
(eChipRev < 40))
#define ASIC_REV_IS_FIJI_P(eChipRev) ((eChipRev >= VI_FIJI_P_A0) && \
(eChipRev < 80))
#define ASIC_REV_IS_POLARIS10_P(eChipRev) ((eChipRev >= VI_POLARIS10_P_A0) && \
(eChipRev < VI_POLARIS11_M_A0))
#define ASIC_REV_IS_POLARIS11_M(eChipRev) (eChipRev >= VI_POLARIS11_M_A0)
/* DCE11 */
#define CZ_CARRIZO_A0 0x01
#define STONEY_A0 0x61
#define CZ_UNKNOWN 0xFF
#define ASIC_REV_IS_STONEY(rev) \
((rev >= STONEY_A0) && (rev < CZ_UNKNOWN))
/*
* ASIC chip ID
*/
/* DCE80 */
#define DEVICE_ID_KALINDI_9834 0x9834
#define DEVICE_ID_TEMASH_9839 0x9839
#define DEVICE_ID_TEMASH_983D 0x983D
/* Asic Family IDs for different asic family. */
#define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */
#define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */
#define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */
#define FAMILY_CZ 135 /* Carrizo */
#define FAMILY_UNKNOWN 0xFF
#endif /* __DAL_ASIC_ID_H__ */

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_REGISTER_LOGGER__
#define __DAL_REGISTER_LOGGER__
/****************
* API functions
***************/
/* dal_reg_logger_push - begin Register Logging */
void dal_reg_logger_push(const char *caller_func);
/* dal_reg_logger_pop - stop Register Logging */
void dal_reg_logger_pop(void);
/* for internal use of the Logger only */
void dal_reg_logger_rw_count_increment(void);
bool dal_reg_logger_should_dump_register(void);
#endif /* __DAL_REGISTER_LOGGER__ */

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_TYPES_H__
#define __DAL_TYPES_H__
#include "signal_types.h"
#include "dc_types.h"
struct dal_logger;
struct dc_bios;
enum dce_version {
DCE_VERSION_UNKNOWN = (-1),
DCE_VERSION_8_0,
DCE_VERSION_10_0,
DCE_VERSION_11_0,
DCE_VERSION_11_2,
DCE_VERSION_MAX,
};
#endif /* __DAL_TYPES_H__ */

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_DDC_SERVICE_TYPES_H__
#define __DAL_DDC_SERVICE_TYPES_H__
#define DP_BRANCH_DEVICE_ID_1 0x0010FA
#define DP_BRANCH_DEVICE_ID_2 0x0022B9
#define DP_SINK_DEVICE_ID_1 0x4CE000
#define DP_BRANCH_DEVICE_ID_3 0x00001A
#define DP_BRANCH_DEVICE_ID_4 0x0080e1
#define DP_BRANCH_DEVICE_ID_5 0x006037
#define DP_SINK_DEVICE_ID_2 0x001CF8
enum ddc_result {
DDC_RESULT_UNKNOWN = 0,
DDC_RESULT_SUCESSFULL,
DDC_RESULT_FAILED_CHANNEL_BUSY,
DDC_RESULT_FAILED_TIMEOUT,
DDC_RESULT_FAILED_PROTOCOL_ERROR,
DDC_RESULT_FAILED_NACK,
DDC_RESULT_FAILED_INCOMPLETE,
DDC_RESULT_FAILED_OPERATION,
DDC_RESULT_FAILED_INVALID_OPERATION,
DDC_RESULT_FAILED_BUFFER_OVERFLOW
};
enum ddc_service_type {
DDC_SERVICE_TYPE_CONNECTOR,
DDC_SERVICE_TYPE_DISPLAY_PORT_MST,
};
enum dcs_dpcd_revision {
DCS_DPCD_REV_10 = 0x10,
DCS_DPCD_REV_11 = 0x11,
DCS_DPCD_REV_12 = 0x12
};
/**
* display sink capability
*/
struct display_sink_capability {
/* dongle type (DP converter, CV smart dongle) */
enum display_dongle_type dongle_type;
/**********************************************************
capabilities going INTO SINK DEVICE (stream capabilities)
**********************************************************/
/* Dongle's downstream count. */
uint32_t downstrm_sink_count;
/* Is dongle's downstream count info field (downstrm_sink_count)
* valid. */
bool downstrm_sink_count_valid;
/* Maximum additional audio delay in microsecond (us) */
uint32_t additional_audio_delay;
/* Audio latency value in microsecond (us) */
uint32_t audio_latency;
/* Interlace video latency value in microsecond (us) */
uint32_t video_latency_interlace;
/* Progressive video latency value in microsecond (us) */
uint32_t video_latency_progressive;
/* Dongle caps: Maximum pixel clock supported over dongle for HDMI */
uint32_t max_hdmi_pixel_clock;
/* Dongle caps: Maximum deep color supported over dongle for HDMI */
enum dc_color_depth max_hdmi_deep_color;
/************************************************************
capabilities going OUT OF SOURCE DEVICE (link capabilities)
************************************************************/
/* support for Spread Spectrum(SS) */
bool ss_supported;
/* DP link settings (laneCount, linkRate, Spread) */
uint32_t dp_link_lane_count;
uint32_t dp_link_rate;
uint32_t dp_link_spead;
enum dcs_dpcd_revision dpcd_revision;
/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
bool is_dp_hdmi_s3d_converter;
/* to check if we have queried the display capability
* for eDP panel already. */
bool is_edp_sink_cap_valid;
enum ddc_transaction_type transaction_type;
enum signal_type signal;
};
struct av_sync_data {
uint8_t av_granularity;/* DPCD 00023h */
uint8_t aud_dec_lat1;/* DPCD 00024h */
uint8_t aud_dec_lat2;/* DPCD 00025h */
uint8_t aud_pp_lat1;/* DPCD 00026h */
uint8_t aud_pp_lat2;/* DPCD 00027h */
uint8_t vid_inter_lat;/* DPCD 00028h */
uint8_t vid_prog_lat;/* DPCD 00029h */
uint8_t aud_del_ins1;/* DPCD 0002Bh */
uint8_t aud_del_ins2;/* DPCD 0002Ch */
uint8_t aud_del_ins3;/* DPCD 0002Dh */
};
/** EDID retrieval related constants, also used by MstMgr **/
#define DDC_EDID_SEGMENT_SIZE 256
#define DDC_EDID_BLOCK_SIZE 128
#define DDC_EDID_BLOCKS_PER_SEGMENT \
(DDC_EDID_SEGMENT_SIZE / DDC_EDID_BLOCK_SIZE)
#define DDC_EDID_EXT_COUNT_OFFSET 0x7E
#define DDC_EDID_ADDRESS_START 0x50
#define DDC_EDID_ADDRESS_END 0x52
#define DDC_EDID_SEGMENT_ADDRESS 0x30
/* signatures for Edid 1x */
#define DDC_EDID1X_VENDORID_SIGNATURE_OFFSET 8
#define DDC_EDID1X_VENDORID_SIGNATURE_LEN 4
#define DDC_EDID1X_EXT_CNT_AND_CHECKSUM_OFFSET 126
#define DDC_EDID1X_EXT_CNT_AND_CHECKSUM_LEN 2
#define DDC_EDID1X_CHECKSUM_OFFSET 127
/* signatures for Edid 20*/
#define DDC_EDID_20_SIGNATURE_OFFSET 0
#define DDC_EDID_20_SIGNATURE 0x20
#define DDC_EDID20_VENDORID_SIGNATURE_OFFSET 1
#define DDC_EDID20_VENDORID_SIGNATURE_LEN 4
#define DDC_EDID20_CHECKSUM_OFFSET 255
#define DDC_EDID20_CHECKSUM_LEN 1
/*DP to VGA converter*/
static const uint8_t DP_VGA_CONVERTER_ID_1[] = "mVGAa";
/*DP to Dual link DVI converter*/
static const uint8_t DP_DVI_CONVERTER_ID_1[] = "m2DVIa";
/*Travis*/
static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
/*Nutmeg*/
static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
/*DP to VGA converter*/
static const uint8_t DP_VGA_CONVERTER_ID_4[] = "DpVga";
/*DP to Dual link DVI converter*/
static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
/*DP to Dual link DVI converter 2*/
static const uint8_t DP_DVI_CONVERTER_ID_42[] = "v2DVIa";
static const uint8_t DP_SINK_DEV_STRING_ID2_REV0[] = "\0\0\0\0\0\0";
/* Identifies second generation PSR TCON from Parade: Device ID string:
* yy-xx-**-**-**-**
*/
/* xx - Hw ID high byte */
static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_HIGH_BYTE =
0x06;
/* yy - HW ID low byte, the same silicon has several package/feature flavors */
static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE1 =
0x61;
static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE2 =
0x62;
static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE3 =
0x63;
static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE4 =
0x72;
static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE5 =
0x73;
#endif /* __DAL_DDC_SERVICE_TYPES_H__ */

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DISPLAY_CLOCK_INTERFACE_H__
#define __DISPLAY_CLOCK_INTERFACE_H__
#include "hw_sequencer_types.h"
#include "grph_object_defs.h"
#include "signal_types.h"
/* Timing related information*/
struct dc_timing_params {
uint32_t INTERLACED:1;
uint32_t HCOUNT_BY_TWO:1;
uint32_t PIXEL_REPETITION:4; /*< values 1 to 10 supported*/
uint32_t PREFETCH:1;
uint32_t h_total;
uint32_t h_addressable;
uint32_t h_sync_width;
};
/* Scaling related information*/
struct dc_scaling_params {
uint32_t h_overscan_right;
uint32_t h_overscan_left;
uint32_t h_taps;
uint32_t v_taps;
};
/* VScalerEfficiency */
enum v_scaler_efficiency {
V_SCALER_EFFICIENCY_LB36BPP = 0,
V_SCALER_EFFICIENCY_LB30BPP = 1,
V_SCALER_EFFICIENCY_LB24BPP = 2,
V_SCALER_EFFICIENCY_LB18BPP = 3
};
/* Parameters required for minimum Engine
* and minimum Display clock calculations*/
struct min_clock_params {
uint32_t id;
uint32_t requested_pixel_clock; /* in KHz */
uint32_t actual_pixel_clock; /* in KHz */
struct view source_view;
struct view dest_view;
struct dc_timing_params timing_info;
struct dc_scaling_params scaling_info;
enum signal_type signal_type;
enum dc_color_depth deep_color_depth;
enum v_scaler_efficiency scaler_efficiency;
bool line_buffer_prefetch_enabled;
};
/* Result of Minimum System and Display clock calculations.
* Minimum System clock and Display clock, source and path to be used
* for Display clock*/
struct minimum_clocks_calculation_result {
uint32_t min_sclk_khz;
uint32_t min_dclk_khz;
uint32_t min_mclk_khz;
uint32_t min_deep_sleep_sclk;
};
/* Enumeration of all clocks states */
enum clocks_state {
CLOCKS_STATE_INVALID = 0,
CLOCKS_STATE_ULTRA_LOW,
CLOCKS_STATE_LOW,
CLOCKS_STATE_NOMINAL,
CLOCKS_STATE_PERFORMANCE,
/* Starting from DCE11, Max 8 level DPM state supported */
CLOCKS_DPM_STATE_LEVEL_INVALID = CLOCKS_STATE_INVALID,
CLOCKS_DPM_STATE_LEVEL_0 = CLOCKS_STATE_ULTRA_LOW,
CLOCKS_DPM_STATE_LEVEL_1 = CLOCKS_STATE_LOW,
CLOCKS_DPM_STATE_LEVEL_2 = CLOCKS_STATE_NOMINAL,
CLOCKS_DPM_STATE_LEVEL_3 = CLOCKS_STATE_PERFORMANCE,
CLOCKS_DPM_STATE_LEVEL_4 = CLOCKS_DPM_STATE_LEVEL_3 + 1,
CLOCKS_DPM_STATE_LEVEL_5 = CLOCKS_DPM_STATE_LEVEL_4 + 1,
CLOCKS_DPM_STATE_LEVEL_6 = CLOCKS_DPM_STATE_LEVEL_5 + 1,
CLOCKS_DPM_STATE_LEVEL_7 = CLOCKS_DPM_STATE_LEVEL_6 + 1,
};
/* Structure containing all state-dependent clocks
* (dependent on "enum clocks_state") */
struct state_dependent_clocks {
uint32_t display_clk_khz;
uint32_t pixel_clk_khz;
};
struct display_clock_state {
uint32_t DFS_BYPASS_ACTIVE:1;
};
struct display_clock;
struct display_clock *dal_display_clock_dce112_create(
struct dc_context *ctx);
struct display_clock *dal_display_clock_dce110_create(
struct dc_context *ctx);
struct display_clock *dal_display_clock_dce80_create(
struct dc_context *ctx);
void dal_display_clock_destroy(struct display_clock **to_destroy);
bool dal_display_clock_validate(
struct display_clock *disp_clk,
struct min_clock_params *params);
uint32_t dal_display_clock_calculate_min_clock(
struct display_clock *disp_clk,
uint32_t path_num,
struct min_clock_params *params);
uint32_t dal_display_clock_get_validation_clock(struct display_clock *disp_clk);
void dal_display_clock_set_clock(
struct display_clock *disp_clk,
uint32_t requested_clock_khz);
uint32_t dal_display_clock_get_clock(struct display_clock *disp_clk);
bool dal_display_clock_get_min_clocks_state(
struct display_clock *disp_clk,
enum clocks_state *clocks_state);
bool dal_display_clock_get_required_clocks_state(
struct display_clock *disp_clk,
struct state_dependent_clocks *req_clocks,
enum clocks_state *clocks_state);
bool dal_display_clock_set_min_clocks_state(
struct display_clock *disp_clk,
enum clocks_state clocks_state);
uint32_t dal_display_clock_get_dp_ref_clk_frequency(
struct display_clock *disp_clk);
/*the second parameter of "switchreferenceclock" is
* a dummy argument for all pre dce 6.0 versions*/
void dal_display_clock_switch_reference_clock(
struct display_clock *disp_clk,
bool use_external_ref_clk,
uint32_t requested_clock_khz);
void dal_display_clock_set_dp_ref_clock_source(
struct display_clock *disp_clk,
enum clock_source_id clk_src);
void dal_display_clock_store_max_clocks_state(
struct display_clock *disp_clk,
enum clocks_state max_clocks_state);
void dal_display_clock_set_clock_state(
struct display_clock *disp_clk,
struct display_clock_state clk_state);
struct display_clock_state dal_display_clock_get_clock_state(
struct display_clock *disp_clk);
uint32_t dal_display_clock_get_dfs_bypass_threshold(
struct display_clock *disp_clk);
void dal_display_clock_invalid_clock_state(
struct display_clock *disp_clk);
#endif /* __DISPLAY_CLOCK_INTERFACE_H__ */

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_DPCD_DEFS_H__
#define __DAL_DPCD_DEFS_H__
enum dpcd_address {
/* addresses marked with 1.2 are only defined since DP 1.2 spec */
/* Reciever Capability Field */
DPCD_ADDRESS_DPCD_REV = 0x00000,
DPCD_ADDRESS_MAX_LINK_RATE = 0x00001,
DPCD_ADDRESS_MAX_LANE_COUNT = 0x00002,
DPCD_ADDRESS_MAX_DOWNSPREAD = 0x00003,
DPCD_ADDRESS_NORP = 0x00004,
DPCD_ADDRESS_DOWNSTREAM_PORT_PRESENT = 0x00005,
DPCD_ADDRESS_MAIN_LINK_CHANNEL_CODING = 0x00006,
DPCD_ADDRESS_DOWNSTREAM_PORT_COUNT = 0x00007,
DPCD_ADDRESS_RECEIVE_PORT0_CAP0 = 0x00008,
DPCD_ADDRESS_RECEIVE_PORT0_CAP1 = 0x00009,
DPCD_ADDRESS_RECEIVE_PORT1_CAP0 = 0x0000A,
DPCD_ADDRESS_RECEIVE_PORT1_CAP1 = 0x0000B,
DPCD_ADDRESS_I2C_SPEED_CNTL_CAP = 0x0000C,/*1.2*/
DPCD_ADDRESS_EDP_CONFIG_CAP = 0x0000D,/*1.2*/
DPCD_ADDRESS_TRAINING_AUX_RD_INTERVAL = 0x000E,/*1.2*/
DPCD_ADDRESS_MSTM_CAP = 0x00021,/*1.2*/
/* Audio Video Sync Data Feild */
DPCD_ADDRESS_AV_GRANULARITY = 0x0023,
DPCD_ADDRESS_AUDIO_DECODE_LATENCY1 = 0x0024,
DPCD_ADDRESS_AUDIO_DECODE_LATENCY2 = 0x0025,
DPCD_ADDRESS_AUDIO_POSTPROCESSING_LATENCY1 = 0x0026,
DPCD_ADDRESS_AUDIO_POSTPROCESSING_LATENCY2 = 0x0027,
DPCD_ADDRESS_VIDEO_INTERLACED_LATENCY = 0x0028,
DPCD_ADDRESS_VIDEO_PROGRESSIVE_LATENCY = 0x0029,
DPCD_ADDRESS_AUDIO_DELAY_INSERT1 = 0x0002B,
DPCD_ADDRESS_AUDIO_DELAY_INSERT2 = 0x0002C,
DPCD_ADDRESS_AUDIO_DELAY_INSERT3 = 0x0002D,
/* Audio capability */
DPCD_ADDRESS_NUM_OF_AUDIO_ENDPOINTS = 0x00022,
DPCD_ADDRESS_GUID_START = 0x00030,/*1.2*/
DPCD_ADDRESS_GUID_END = 0x0003f,/*1.2*/
DPCD_ADDRESS_PSR_SUPPORT_VER = 0x00070,
DPCD_ADDRESS_PSR_CAPABILITY = 0x00071,
DPCD_ADDRESS_DWN_STRM_PORT0_CAPS = 0x00080,/*1.2a*/
/* Link Configuration Field */
DPCD_ADDRESS_LINK_BW_SET = 0x00100,
DPCD_ADDRESS_LANE_COUNT_SET = 0x00101,
DPCD_ADDRESS_TRAINING_PATTERN_SET = 0x00102,
DPCD_ADDRESS_LANE0_SET = 0x00103,
DPCD_ADDRESS_LANE1_SET = 0x00104,
DPCD_ADDRESS_LANE2_SET = 0x00105,
DPCD_ADDRESS_LANE3_SET = 0x00106,
DPCD_ADDRESS_DOWNSPREAD_CNTL = 0x00107,
DPCD_ADDRESS_I2C_SPEED_CNTL = 0x00109,/*1.2*/
DPCD_ADDRESS_EDP_CONFIG_SET = 0x0010A,
DPCD_ADDRESS_LINK_QUAL_LANE0_SET = 0x0010B,
DPCD_ADDRESS_LINK_QUAL_LANE1_SET = 0x0010C,
DPCD_ADDRESS_LINK_QUAL_LANE2_SET = 0x0010D,
DPCD_ADDRESS_LINK_QUAL_LANE3_SET = 0x0010E,
DPCD_ADDRESS_LANE0_SET2 = 0x0010F,/*1.2*/
DPCD_ADDRESS_LANE2_SET2 = 0x00110,/*1.2*/
DPCD_ADDRESS_MSTM_CNTL = 0x00111,/*1.2*/
DPCD_ADDRESS_PSR_ENABLE_CFG = 0x0170,
/* Payload Table Configuration Field 1.2 */
DPCD_ADDRESS_PAYLOAD_ALLOCATE_SET = 0x001C0,
DPCD_ADDRESS_PAYLOAD_ALLOCATE_START_TIMESLOT = 0x001C1,
DPCD_ADDRESS_PAYLOAD_ALLOCATE_TIMESLOT_COUNT = 0x001C2,
DPCD_ADDRESS_SINK_COUNT = 0x0200,
DPCD_ADDRESS_DEVICE_SERVICE_IRQ_VECTOR = 0x0201,
/* Link / Sink Status Field */
DPCD_ADDRESS_LANE_01_STATUS = 0x00202,
DPCD_ADDRESS_LANE_23_STATUS = 0x00203,
DPCD_ADDRESS_LANE_ALIGN_STATUS_UPDATED = 0x0204,
DPCD_ADDRESS_SINK_STATUS = 0x0205,
/* Adjust Request Field */
DPCD_ADDRESS_ADJUST_REQUEST_LANE0_1 = 0x0206,
DPCD_ADDRESS_ADJUST_REQUEST_LANE2_3 = 0x0207,
DPCD_ADDRESS_ADJUST_REQUEST_POST_CURSOR2 = 0x020C,
/* Test Request Field */
DPCD_ADDRESS_TEST_REQUEST = 0x0218,
DPCD_ADDRESS_TEST_LINK_RATE = 0x0219,
DPCD_ADDRESS_TEST_LANE_COUNT = 0x0220,
DPCD_ADDRESS_TEST_PATTERN = 0x0221,
DPCD_ADDRESS_TEST_MISC1 = 0x0232,
/* Phy Test Pattern Field */
DPCD_ADDRESS_TEST_PHY_PATTERN = 0x0248,
DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_7_0 = 0x0250,
DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_15_8 = 0x0251,
DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_23_16 = 0x0252,
DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_31_24 = 0x0253,
DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_39_32 = 0x0254,
DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_47_40 = 0x0255,
DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_55_48 = 0x0256,
DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_63_56 = 0x0257,
DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_71_64 = 0x0258,
DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_79_72 = 0x0259,
/* Test Response Field*/
DPCD_ADDRESS_TEST_RESPONSE = 0x0260,
/* Audio Test Pattern Field 1.2*/
DPCD_ADDRESS_TEST_AUDIO_MODE = 0x0271,
DPCD_ADDRESS_TEST_AUDIO_PATTERN_TYPE = 0x0272,
DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_1 = 0x0273,
DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_2 = 0x0274,
DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_3 = 0x0275,
DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_4 = 0x0276,
DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_5 = 0x0277,
DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_6 = 0x0278,
DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_7 = 0x0279,
DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_8 = 0x027A,
/* Payload Table Status Field */
DPCD_ADDRESS_PAYLOAD_TABLE_UPDATE_STATUS = 0x002C0,/*1.2*/
DPCD_ADDRESS_VC_PAYLOAD_ID_SLOT1 = 0x002C1,/*1.2*/
DPCD_ADDRESS_VC_PAYLOAD_ID_SLOT63 = 0x002FF,/*1.2*/
/* Source Device Specific Field */
DPCD_ADDRESS_SOURCE_DEVICE_ID_START = 0x0300,
DPCD_ADDRESS_SOURCE_DEVICE_ID_END = 0x0301,
DPCD_ADDRESS_AMD_INTERNAL_DEBUG_START = 0x030C,
DPCD_ADDRESS_AMD_INTERNAL_DEBUG_END = 0x030F,
DPCD_ADDRESS_SOURCE_SPECIFIC_TABLE_START = 0x0310,
DPCD_ADDRESS_SOURCE_SPECIFIC_TABLE_END = 0x037F,
DPCD_ADDRESS_SOURCE_RESERVED_START = 0x0380,
DPCD_ADDRESS_SOURCE_RESERVED_END = 0x03FF,
/* Sink Device Specific Field */
DPCD_ADDRESS_SINK_DEVICE_ID_START = 0x0400,
DPCD_ADDRESS_SINK_DEVICE_ID_END = 0x0402,
DPCD_ADDRESS_SINK_DEVICE_STR_START = 0x0403,
DPCD_ADDRESS_SINK_DEVICE_STR_END = 0x0408,
DPCD_ADDRESS_SINK_REVISION_START = 0x409,
DPCD_ADDRESS_SINK_REVISION_END = 0x40B,
/* Branch Device Specific Field */
DPCD_ADDRESS_BRANCH_DEVICE_ID_START = 0x0500,
DPCD_ADDRESS_BRANCH_DEVICE_ID_END = 0x0502,
DPCD_ADDRESS_BRANCH_DEVICE_STR_START = 0x0503,
DPCD_ADDRESS_BRANCH_DEVICE_STR_END = 0x0508,
DPCD_ADDRESS_BRANCH_REVISION_START = 0x0509,
DPCD_ADDRESS_BRANCH_REVISION_END = 0x050B,
DPCD_ADDRESS_POWER_STATE = 0x0600,
/* EDP related */
DPCD_ADDRESS_EDP_REV = 0x0700,
DPCD_ADDRESS_EDP_CAPABILITY = 0x0701,
DPCD_ADDRESS_EDP_BACKLIGHT_ADJUST_CAP = 0x0702,
DPCD_ADDRESS_EDP_GENERAL_CAP2 = 0x0703,
DPCD_ADDRESS_EDP_DISPLAY_CONTROL = 0x0720,
DPCD_ADDRESS_SUPPORTED_LINK_RATES = 0x00010, /* edp 1.4 */
DPCD_ADDRESS_EDP_BACKLIGHT_SET = 0x0721,
DPCD_ADDRESS_EDP_BACKLIGHT_BRIGHTNESS_MSB = 0x0722,
DPCD_ADDRESS_EDP_BACKLIGHT_BRIGHTNESS_LSB = 0x0723,
DPCD_ADDRESS_EDP_PWMGEN_BIT_COUNT = 0x0724,
DPCD_ADDRESS_EDP_PWMGEN_BIT_COUNT_CAP_MIN = 0x0725,
DPCD_ADDRESS_EDP_PWMGEN_BIT_COUNT_CAP_MAX = 0x0726,
DPCD_ADDRESS_EDP_BACKLIGHT_CONTROL_STATUS = 0x0727,
DPCD_ADDRESS_EDP_BACKLIGHT_FREQ_SET = 0x0728,
DPCD_ADDRESS_EDP_REVERVED = 0x0729,
DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MIN_MSB = 0x072A,
DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MIN_MID = 0x072B,
DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MIN_LSB = 0x072C,
DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MAX_MSB = 0x072D,
DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MAX_MID = 0x072E,
DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MAX_LSB = 0x072F,
DPCD_ADDRESS_EDP_DBC_MINIMUM_BRIGHTNESS_SET = 0x0732,
DPCD_ADDRESS_EDP_DBC_MAXIMUM_BRIGHTNESS_SET = 0x0733,
/* Sideband MSG Buffers 1.2 */
DPCD_ADDRESS_DOWN_REQ_START = 0x01000,
DPCD_ADDRESS_DOWN_REQ_END = 0x011ff,
DPCD_ADDRESS_UP_REP_START = 0x01200,
DPCD_ADDRESS_UP_REP_END = 0x013ff,
DPCD_ADDRESS_DOWN_REP_START = 0x01400,
DPCD_ADDRESS_DOWN_REP_END = 0x015ff,
DPCD_ADDRESS_UP_REQ_START = 0x01600,
DPCD_ADDRESS_UP_REQ_END = 0x017ff,
/* ESI (Event Status Indicator) Field 1.2 */
DPCD_ADDRESS_SINK_COUNT_ESI = 0x02002,
DPCD_ADDRESS_DEVICE_IRQ_ESI0 = 0x02003,
DPCD_ADDRESS_DEVICE_IRQ_ESI1 = 0x02004,
/*@todo move dpcd_address_Lane01Status back here*/
DPCD_ADDRESS_PSR_ERROR_STATUS = 0x2006,
DPCD_ADDRESS_PSR_EVENT_STATUS = 0x2007,
DPCD_ADDRESS_PSR_SINK_STATUS = 0x2008,
DPCD_ADDRESS_PSR_DBG_REGISTER0 = 0x2009,
DPCD_ADDRESS_PSR_DBG_REGISTER1 = 0x200A,
DPCD_ADDRESS_DP13_DPCD_REV = 0x2200,
DPCD_ADDRESS_DP13_MAX_LINK_RATE = 0x2201,
/* Travis specific addresses */
DPCD_ADDRESS_TRAVIS_SINK_DEV_SEL = 0x5f0,
DPCD_ADDRESS_TRAVIS_SINK_ACCESS_OFFSET = 0x5f1,
DPCD_ADDRESS_TRAVIS_SINK_ACCESS_REG = 0x5f2,
};
enum dpcd_revision {
DPCD_REV_10 = 0x10,
DPCD_REV_11 = 0x11,
DPCD_REV_12 = 0x12,
DPCD_REV_13 = 0x13,
DPCD_REV_14 = 0x14
};
enum dp_pwr_state {
DP_PWR_STATE_D0 = 1,/* direct HW translation! */
DP_PWR_STATE_D3
};
/* these are the types stored at DOWNSTREAMPORT_PRESENT */
enum dpcd_downstream_port_type {
DOWNSTREAM_DP = 0,
DOWNSTREAM_VGA,
DOWNSTREAM_DVI_HDMI,
DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */
};
enum dpcd_link_test_patterns {
LINK_TEST_PATTERN_NONE = 0,
LINK_TEST_PATTERN_COLOR_RAMP,
LINK_TEST_PATTERN_VERTICAL_BARS,
LINK_TEST_PATTERN_COLOR_SQUARES
};
enum dpcd_test_color_format {
TEST_COLOR_FORMAT_RGB = 0,
TEST_COLOR_FORMAT_YCBCR422,
TEST_COLOR_FORMAT_YCBCR444
};
enum dpcd_test_bit_depth {
TEST_BIT_DEPTH_6 = 0,
TEST_BIT_DEPTH_8,
TEST_BIT_DEPTH_10,
TEST_BIT_DEPTH_12,
TEST_BIT_DEPTH_16
};
/* PHY (encoder) test patterns
The order of test patterns follows DPCD register PHY_TEST_PATTERN (0x248)
*/
enum dpcd_phy_test_patterns {
PHY_TEST_PATTERN_NONE = 0,
PHY_TEST_PATTERN_D10_2,
PHY_TEST_PATTERN_SYMBOL_ERROR,
PHY_TEST_PATTERN_PRBS7,
PHY_TEST_PATTERN_80BIT_CUSTOM,/* For DP1.2 only */
PHY_TEST_PATTERN_HBR2_COMPLIANCE_EYE/* For DP1.2 only */
};
enum dpcd_test_dyn_range {
TEST_DYN_RANGE_VESA = 0,
TEST_DYN_RANGE_CEA
};
enum dpcd_audio_test_pattern {
AUDIO_TEST_PATTERN_OPERATOR_DEFINED = 0,/* direct HW translation */
AUDIO_TEST_PATTERN_SAWTOOTH
};
enum dpcd_audio_sampling_rate {
AUDIO_SAMPLING_RATE_32KHZ = 0,/* direct HW translation */
AUDIO_SAMPLING_RATE_44_1KHZ,
AUDIO_SAMPLING_RATE_48KHZ,
AUDIO_SAMPLING_RATE_88_2KHZ,
AUDIO_SAMPLING_RATE_96KHZ,
AUDIO_SAMPLING_RATE_176_4KHZ,
AUDIO_SAMPLING_RATE_192KHZ
};
enum dpcd_audio_channels {
AUDIO_CHANNELS_1 = 0,/* direct HW translation */
AUDIO_CHANNELS_2,
AUDIO_CHANNELS_3,
AUDIO_CHANNELS_4,
AUDIO_CHANNELS_5,
AUDIO_CHANNELS_6,
AUDIO_CHANNELS_7,
AUDIO_CHANNELS_8,
AUDIO_CHANNELS_COUNT
};
enum dpcd_audio_test_pattern_periods {
DPCD_AUDIO_TEST_PATTERN_PERIOD_NOTUSED = 0,/* direct HW translation */
DPCD_AUDIO_TEST_PATTERN_PERIOD_3,
DPCD_AUDIO_TEST_PATTERN_PERIOD_6,
DPCD_AUDIO_TEST_PATTERN_PERIOD_12,
DPCD_AUDIO_TEST_PATTERN_PERIOD_24,
DPCD_AUDIO_TEST_PATTERN_PERIOD_48,
DPCD_AUDIO_TEST_PATTERN_PERIOD_96,
DPCD_AUDIO_TEST_PATTERN_PERIOD_192,
DPCD_AUDIO_TEST_PATTERN_PERIOD_384,
DPCD_AUDIO_TEST_PATTERN_PERIOD_768,
DPCD_AUDIO_TEST_PATTERN_PERIOD_1536
};
/* This enum is for programming DPCD TRAINING_PATTERN_SET */
enum dpcd_training_patterns {
DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,/* direct HW translation! */
DPCD_TRAINING_PATTERN_1,
DPCD_TRAINING_PATTERN_2,
DPCD_TRAINING_PATTERN_3,
DPCD_TRAINING_PATTERN_4 = 7
};
/* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus
It defines the possible PSR states. */
enum dpcd_psr_sink_states {
PSR_SINK_STATE_INACTIVE = 0,
PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING = 1,
PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB = 2,
PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING = 3,
PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC = 4,
PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7,
};
/* This enum defines the Panel's eDP revision at DPCD 700h
* 00h = eDP v1.1 or lower
* 01h = eDP v1.2
* 02h = eDP v1.3 (PSR support starts here)
* 03h = eDP v1.4
* If unknown revision, treat as eDP v1.1, meaning least functionality set.
* This enum has values matched to eDP spec, thus values should not change.
*/
enum dpcd_edp_revision {
DPCD_EDP_REVISION_EDP_V1_1 = 0,
DPCD_EDP_REVISION_EDP_V1_2 = 1,
DPCD_EDP_REVISION_EDP_V1_3 = 2,
DPCD_EDP_REVISION_EDP_V1_4 = 3,
DPCD_EDP_REVISION_EDP_UNKNOWN = DPCD_EDP_REVISION_EDP_V1_1,
};
union dpcd_rev {
struct {
uint8_t MINOR:4;
uint8_t MAJOR:4;
} bits;
uint8_t raw;
};
union max_lane_count {
struct {
uint8_t MAX_LANE_COUNT:5;
uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;
uint8_t TPS3_SUPPORTED:1;
uint8_t ENHANCED_FRAME_CAP:1;
} bits;
uint8_t raw;
};
union max_down_spread {
struct {
uint8_t MAX_DOWN_SPREAD:1;
uint8_t RESERVED:5;
uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1;
uint8_t TPS4_SUPPORTED:1;
} bits;
uint8_t raw;
};
union mstm_cap {
struct {
uint8_t MST_CAP:1;
uint8_t RESERVED:7;
} bits;
uint8_t raw;
};
union lane_count_set {
struct {
uint8_t LANE_COUNT_SET:5;
uint8_t POST_LT_ADJ_REQ_GRANTED:1;
uint8_t RESERVED:1;
uint8_t ENHANCED_FRAMING:1;
} bits;
uint8_t raw;
};
union lane_status {
struct {
uint8_t CR_DONE_0:1;
uint8_t CHANNEL_EQ_DONE_0:1;
uint8_t SYMBOL_LOCKED_0:1;
uint8_t RESERVED0:1;
uint8_t CR_DONE_1:1;
uint8_t CHANNEL_EQ_DONE_1:1;
uint8_t SYMBOL_LOCKED_1:1;
uint8_t RESERVED_1:1;
} bits;
uint8_t raw;
};
union device_service_irq {
struct {
uint8_t REMOTE_CONTROL_CMD_PENDING:1;
uint8_t AUTOMATED_TEST:1;
uint8_t CP_IRQ:1;
uint8_t MCCS_IRQ:1;
uint8_t DOWN_REP_MSG_RDY:1;
uint8_t UP_REQ_MSG_RDY:1;
uint8_t SINK_SPECIFIC:1;
uint8_t reserved:1;
} bits;
uint8_t raw;
};
union sink_count {
struct {
uint8_t SINK_COUNT:6;
uint8_t CPREADY:1;
uint8_t RESERVED:1;
} bits;
uint8_t raw;
};
union lane_align_status_updated {
struct {
uint8_t INTERLANE_ALIGN_DONE:1;
uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1;
uint8_t RESERVED:4;
uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1;
uint8_t LINK_STATUS_UPDATED:1;
} bits;
uint8_t raw;
};
union lane_adjust {
struct {
uint8_t VOLTAGE_SWING_LANE:2;
uint8_t PRE_EMPHASIS_LANE:2;
uint8_t RESERVED:4;
} bits;
uint8_t raw;
};
union dpcd_training_pattern {
struct {
uint8_t TRAINING_PATTERN_SET:4;
uint8_t RECOVERED_CLOCK_OUT_EN:1;
uint8_t SCRAMBLING_DISABLE:1;
uint8_t SYMBOL_ERROR_COUNT_SEL:2;
} v1_4;
struct {
uint8_t TRAINING_PATTERN_SET:2;
uint8_t LINK_QUAL_PATTERN_SET:2;
uint8_t RESERVED:4;
} v1_3;
uint8_t raw;
};
/* Training Lane is used to configure downstream DP device's voltage swing
and pre-emphasis levels*/
/* The DPCD addresses are from 0x103 to 0x106*/
union dpcd_training_lane {
struct {
uint8_t VOLTAGE_SWING_SET:2;
uint8_t MAX_SWING_REACHED:1;
uint8_t PRE_EMPHASIS_SET:2;
uint8_t MAX_PRE_EMPHASIS_REACHED:1;
uint8_t RESERVED:2;
} bits;
uint8_t raw;
};
/* TMDS-converter related */
union dwnstream_port_caps_byte0 {
struct {
uint8_t DWN_STRM_PORTX_TYPE:3;
uint8_t DWN_STRM_PORTX_HPD:1;
uint8_t RESERVERD:4;
} bits;
uint8_t raw;
};
/* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/
enum dpcd_downstream_port_detailed_type {
DOWN_STREAM_DETAILED_DP = 0,
DOWN_STREAM_DETAILED_VGA,
DOWN_STREAM_DETAILED_DVI,
DOWN_STREAM_DETAILED_HDMI,
DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/
DOWN_STREAM_DETAILED_DP_PLUS_PLUS
};
union dwnstream_port_caps_byte2 {
struct {
uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
uint8_t RESERVED:6;
} bits;
uint8_t raw;
};
union dp_downstream_port_present {
uint8_t byte;
struct {
uint8_t PORT_PRESENT:1;
uint8_t PORT_TYPE:2;
uint8_t FMT_CONVERSION:1;
uint8_t DETAILED_CAPS:1;
uint8_t RESERVED:3;
} fields;
};
union dwnstream_port_caps_byte3_dvi {
struct {
uint8_t RESERVED1:1;
uint8_t DUAL_LINK:1;
uint8_t HIGH_COLOR_DEPTH:1;
uint8_t RESERVED2:5;
} bits;
uint8_t raw;
};
union dwnstream_port_caps_byte3_hdmi {
struct {
uint8_t FRAME_SEQ_TO_FRAME_PACK:1;
uint8_t RESERVED:7;
} bits;
uint8_t raw;
};
/*4-byte structure for detailed capabilities of a down-stream port
(DP-to-TMDS converter).*/
union sink_status {
struct {
uint8_t RX_PORT0_STATUS:1;
uint8_t RX_PORT1_STATUS:1;
uint8_t RESERVED:6;
} bits;
uint8_t raw;
};
/*6-byte structure corresponding to 6 registers (200h-205h)
read during handling of HPD-IRQ*/
union hpd_irq_data {
struct {
union sink_count sink_cnt;/* 200h */
union device_service_irq device_service_irq;/* 201h */
union lane_status lane01_status;/* 202h */
union lane_status lane23_status;/* 203h */
union lane_align_status_updated lane_status_updated;/* 204h */
union sink_status sink_status;
} bytes;
uint8_t raw[6];
};
union down_stream_port_count {
struct {
uint8_t DOWN_STR_PORT_COUNT:4;
uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/
/*Bit 6 = MSA_TIMING_PAR_IGNORED
0 = Sink device requires the MSA timing parameters
1 = Sink device is capable of rendering incoming video
stream without MSA timing parameters*/
uint8_t IGNORE_MSA_TIMING_PARAM:1;
/*Bit 7 = OUI Support
0 = OUI not supported
1 = OUI supported
(OUI and Device Identification mandatory for DP 1.2)*/
uint8_t OUI_SUPPORT:1;
} bits;
uint8_t raw;
};
union down_spread_ctrl {
struct {
uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/
/* Bits 4 = SPREAD_AMP. Spreading amplitude
0 = Main link signal is not downspread
1 = Main link signal is downspread <= 0.5%
with frequency in the range of 30kHz ~ 33kHz*/
uint8_t SPREAD_AMP:1;
uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/
/*Bit 7 = MSA_TIMING_PAR_IGNORE_EN
0 = Source device will send valid data for the MSA Timing Params
1 = Source device may send invalid data for these MSA Timing Params*/
uint8_t IGNORE_MSA_TIMING_PARAM:1;
} bits;
uint8_t raw;
};
union dpcd_edp_config {
struct {
uint8_t PANEL_MODE_EDP:1;
uint8_t FRAMING_CHANGE_ENABLE:1;
uint8_t RESERVED:5;
uint8_t PANEL_SELF_TEST_ENABLE:1;
} bits;
uint8_t raw;
};
struct dp_device_vendor_id {
uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
};
struct dp_sink_hw_fw_revision {
uint8_t ieee_hw_rev;
uint8_t ieee_fw_rev[2];
};
/*DPCD register of DP receiver capability field bits-*/
union edp_configuration_cap {
struct {
uint8_t ALT_SCRAMBLER_RESET:1;
uint8_t FRAMING_CHANGE:1;
uint8_t RESERVED:1;
uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1;
uint8_t RESERVED2:4;
} bits;
uint8_t raw;
};
union training_aux_rd_interval {
struct {
uint8_t TRAINIG_AUX_RD_INTERVAL:7;
uint8_t EXT_RECIEVER_CAP_FIELD_PRESENT:1;
} bits;
uint8_t raw;
};
/* Automated test structures */
union test_request {
struct {
uint8_t LINK_TRAINING :1;
uint8_t LINK_TEST_PATTRN :1;
uint8_t EDID_REAT :1;
uint8_t PHY_TEST_PATTERN :1;
uint8_t AUDIO_TEST_PATTERN :1;
uint8_t RESERVED :1;
uint8_t TEST_STEREO_3D :1;
} bits;
uint8_t raw;
};
union test_response {
struct {
uint8_t ACK :1;
uint8_t NO_ACK :1;
uint8_t RESERVED :6;
} bits;
uint8_t raw;
};
union phy_test_pattern {
struct {
/* DpcdPhyTestPatterns. This field is 2 bits for DP1.1
* and 3 bits for DP1.2.
*/
uint8_t PATTERN :3;
/* BY speci, bit7:2 is 0 for DP1.1. */
uint8_t RESERVED :5;
} bits;
uint8_t raw;
};
/* States of Compliance Test Specification (CTS DP1.2). */
union compliance_test_state {
struct {
unsigned char STEREO_3D_RUNNING : 1;
unsigned char SET_TEST_PATTERN_PENDING : 1;
unsigned char RESERVED : 6;
} bits;
unsigned char raw;
};
union link_test_pattern {
struct {
/* dpcd_link_test_patterns */
unsigned char PATTERN :2;
unsigned char RESERVED:6;
} bits;
unsigned char raw;
};
union test_misc {
struct dpcd_test_misc_bits {
unsigned char SYNC_CLOCK :1;
/* dpcd_test_color_format */
unsigned char CLR_FORMAT :2;
/* dpcd_test_dyn_range */
unsigned char DYN_RANGE :1;
unsigned char YCBCR :1;
/* dpcd_test_bit_depth */
unsigned char BPC :3;
} bits;
unsigned char raw;
};
#endif /* __DAL_DPCD_DEFS_H__ */

390
drivers/gpu/drm/amd/display/include/fixed31_32.h Normal file
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_FIXED31_32_H__
#define __DAL_FIXED31_32_H__
#include "os_types.h"
/*
* @brief
* Arithmetic operations on real numbers
* represented as fixed-point numbers.
* There are: 1 bit for sign,
* 31 bit for integer part,
* 32 bits for fractional part.
*
* @note
* Currently, overflows and underflows are asserted;
* no special result returned.
*/
struct fixed31_32 {
int64_t value;
};
/*
* @brief
* Useful constants
*/
static const struct fixed31_32 dal_fixed31_32_zero = { 0 };
static const struct fixed31_32 dal_fixed31_32_epsilon = { 1LL };
static const struct fixed31_32 dal_fixed31_32_half = { 0x80000000LL };
static const struct fixed31_32 dal_fixed31_32_one = { 0x100000000LL };
static const struct fixed31_32 dal_fixed31_32_pi = { 13493037705LL };
static const struct fixed31_32 dal_fixed31_32_two_pi = { 26986075409LL };
static const struct fixed31_32 dal_fixed31_32_e = { 11674931555LL };
static const struct fixed31_32 dal_fixed31_32_ln2 = { 2977044471LL };
static const struct fixed31_32 dal_fixed31_32_ln2_div_2 = { 1488522236LL };
/*
* @brief
* Initialization routines
*/
/*
* @brief
* result = numerator / denominator
*/
struct fixed31_32 dal_fixed31_32_from_fraction(
int64_t numerator,
int64_t denominator);
/*
* @brief
* result = arg
*/
struct fixed31_32 dal_fixed31_32_from_int(
int64_t arg);
/*
* @brief
* Unary operators
*/
/*
* @brief
* result = -arg
*/
struct fixed31_32 dal_fixed31_32_neg(
struct fixed31_32 arg);
/*
* @brief
* result = abs(arg) := (arg >= 0) ? arg : -arg
*/
struct fixed31_32 dal_fixed31_32_abs(
struct fixed31_32 arg);
/*
* @brief
* Binary relational operators
*/
/*
* @brief
* result = arg1 < arg2
*/
bool dal_fixed31_32_lt(
struct fixed31_32 arg1,
struct fixed31_32 arg2);
/*
* @brief
* result = arg1 <= arg2
*/
bool dal_fixed31_32_le(
struct fixed31_32 arg1,
struct fixed31_32 arg2);
/*
* @brief
* result = arg1 == arg2
*/
bool dal_fixed31_32_eq(
struct fixed31_32 arg1,
struct fixed31_32 arg2);
/*
* @brief
* result = min(arg1, arg2) := (arg1 <= arg2) ? arg1 : arg2
*/
struct fixed31_32 dal_fixed31_32_min(
struct fixed31_32 arg1,
struct fixed31_32 arg2);
/*
* @brief
* result = max(arg1, arg2) := (arg1 <= arg2) ? arg2 : arg1
*/
struct fixed31_32 dal_fixed31_32_max(
struct fixed31_32 arg1,
struct fixed31_32 arg2);
/*
* @brief
* | min_value, when arg <= min_value
* result = | arg, when min_value < arg < max_value
* | max_value, when arg >= max_value
*/
struct fixed31_32 dal_fixed31_32_clamp(
struct fixed31_32 arg,
struct fixed31_32 min_value,
struct fixed31_32 max_value);
/*
* @brief
* Binary shift operators
*/
/*
* @brief
* result = arg << shift
*/
struct fixed31_32 dal_fixed31_32_shl(
struct fixed31_32 arg,
uint8_t shift);
/*
* @brief
* result = arg >> shift
*/
struct fixed31_32 dal_fixed31_32_shr(
struct fixed31_32 arg,
uint8_t shift);
/*
* @brief
* Binary additive operators
*/
/*
* @brief
* result = arg1 + arg2
*/
struct fixed31_32 dal_fixed31_32_add(
struct fixed31_32 arg1,
struct fixed31_32 arg2);
/*
* @brief
* result = arg1 - arg2
*/
struct fixed31_32 dal_fixed31_32_sub_int(
struct fixed31_32 arg1,
int32_t arg2);
/*
* @brief
* result = arg1 - arg2
*/
struct fixed31_32 dal_fixed31_32_sub(
struct fixed31_32 arg1,
struct fixed31_32 arg2);
/*
* @brief
* Binary multiplicative operators
*/
/*
* @brief
* result = arg1 * arg2
*/
struct fixed31_32 dal_fixed31_32_mul_int(
struct fixed31_32 arg1,
int32_t arg2);
/*
* @brief
* result = arg1 * arg2
*/
struct fixed31_32 dal_fixed31_32_mul(
struct fixed31_32 arg1,
struct fixed31_32 arg2);
/*
* @brief
* result = square(arg) := arg * arg
*/
struct fixed31_32 dal_fixed31_32_sqr(
struct fixed31_32 arg);
/*
* @brief
* result = arg1 / arg2
*/
struct fixed31_32 dal_fixed31_32_div_int(
struct fixed31_32 arg1,
int64_t arg2);
/*
* @brief
* result = arg1 / arg2
*/
struct fixed31_32 dal_fixed31_32_div(
struct fixed31_32 arg1,
struct fixed31_32 arg2);
/*
* @brief
* Reciprocal function
*/
/*
* @brief
* result = reciprocal(arg) := 1 / arg
*
* @note
* No special actions taken in case argument is zero.
*/
struct fixed31_32 dal_fixed31_32_recip(
struct fixed31_32 arg);
/*
* @brief
* Trigonometric functions
*/
/*
* @brief
* result = sinc(arg) := sin(arg) / arg
*
* @note
* Argument specified in radians,
* internally it's normalized to [-2pi...2pi] range.
*/
struct fixed31_32 dal_fixed31_32_sinc(
struct fixed31_32 arg);
/*
* @brief
* result = sin(arg)
*
* @note
* Argument specified in radians,
* internally it's normalized to [-2pi...2pi] range.
*/
struct fixed31_32 dal_fixed31_32_sin(
struct fixed31_32 arg);
/*
* @brief
* result = cos(arg)
*
* @note
* Argument specified in radians
* and should be in [-2pi...2pi] range -
* passing arguments outside that range
* will cause incorrect result!
*/
struct fixed31_32 dal_fixed31_32_cos(
struct fixed31_32 arg);
/*
* @brief
* Transcendent functions
*/
/*
* @brief
* result = exp(arg)
*
* @note
* Currently, function is verified for abs(arg) <= 1.
*/
struct fixed31_32 dal_fixed31_32_exp(
struct fixed31_32 arg);
/*
* @brief
* result = log(arg)
*
* @note
* Currently, abs(arg) should be less than 1.
* No normalization is done.
* Currently, no special actions taken
* in case of invalid argument(s). Take care!
*/
struct fixed31_32 dal_fixed31_32_log(
struct fixed31_32 arg);
/*
* @brief
* Power function
*/
/*
* @brief
* result = pow(arg1, arg2)
*
* @note
* Currently, abs(arg1) should be less than 1. Take care!
*/
struct fixed31_32 dal_fixed31_32_pow(
struct fixed31_32 arg1,
struct fixed31_32 arg2);
/*
* @brief
* Rounding functions
*/
/*
* @brief
* result = floor(arg) := greatest integer lower than or equal to arg
*/
int32_t dal_fixed31_32_floor(
struct fixed31_32 arg);
/*
* @brief
* result = round(arg) := integer nearest to arg
*/
int32_t dal_fixed31_32_round(
struct fixed31_32 arg);
/*
* @brief
* result = ceil(arg) := lowest integer greater than or equal to arg
*/
int32_t dal_fixed31_32_ceil(
struct fixed31_32 arg);
/* the following two function are used in scaler hw programming to convert fixed
* point value to format 2 bits from integer part and 19 bits from fractional
* part. The same applies for u0d19, 0 bits from integer part and 19 bits from
* fractional
*/
uint32_t dal_fixed31_32_u2d19(
struct fixed31_32 arg);
uint32_t dal_fixed31_32_u0d19(
struct fixed31_32 arg);
#endif

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_FIXED32_32_H__
#define __DAL_FIXED32_32_H__
#include "os_types.h"
struct fixed32_32 {
uint64_t value;
};
static const struct fixed32_32 dal_fixed32_32_zero = { 0 };
static const struct fixed32_32 dal_fixed32_32_one = { 0x100000000LL };
static const struct fixed32_32 dal_fixed32_32_half = { 0x80000000LL };
struct fixed32_32 dal_fixed32_32_from_fraction(uint32_t n, uint32_t d);
struct fixed32_32 dal_fixed32_32_from_int(uint32_t value);
struct fixed32_32 dal_fixed32_32_add(
struct fixed32_32 lhs,
struct fixed32_32 rhs);
struct fixed32_32 dal_fixed32_32_add_int(
struct fixed32_32 lhs,
uint32_t rhs);
struct fixed32_32 dal_fixed32_32_sub(
struct fixed32_32 lhs,
struct fixed32_32 rhs);
struct fixed32_32 dal_fixed32_32_sub_int(
struct fixed32_32 lhs,
uint32_t rhs);
struct fixed32_32 dal_fixed32_32_mul(
struct fixed32_32 lhs,
struct fixed32_32 rhs);
struct fixed32_32 dal_fixed32_32_mul_int(
struct fixed32_32 lhs,
uint32_t rhs);
struct fixed32_32 dal_fixed32_32_div(
struct fixed32_32 lhs,
struct fixed32_32 rhs);
struct fixed32_32 dal_fixed32_32_div_int(
struct fixed32_32 lhs,
uint32_t rhs);
struct fixed32_32 dal_fixed32_32_min(
struct fixed32_32 lhs,
struct fixed32_32 rhs);
struct fixed32_32 dal_fixed32_32_max(
struct fixed32_32 lhs,
struct fixed32_32 rhs);
bool dal_fixed32_32_gt(struct fixed32_32 lhs, struct fixed32_32 rhs);
bool dal_fixed32_32_gt_int(struct fixed32_32 lhs, uint32_t rhs);
bool dal_fixed32_32_lt(struct fixed32_32 lhs, struct fixed32_32 rhs);
bool dal_fixed32_32_lt_int(struct fixed32_32 lhs, uint32_t rhs);
bool dal_fixed32_32_le(struct fixed32_32 lhs, struct fixed32_32 rhs);
bool dal_fixed32_32_le_int(struct fixed32_32 lhs, uint32_t rhs);
bool dal_fixed32_32_eq(struct fixed32_32 lhs, struct fixed32_32 rhs);
uint32_t dal_fixed32_32_ceil(struct fixed32_32 value);
uint32_t dal_fixed32_32_floor(struct fixed32_32 value);
uint32_t dal_fixed32_32_round(struct fixed32_32 value);
#endif

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_GPIO_INTERFACE_H__
#define __DAL_GPIO_INTERFACE_H__
#include "gpio_types.h"
#include "grph_object_defs.h"
struct gpio;
/* Open the handle for future use */
enum gpio_result dal_gpio_open(
struct gpio *gpio,
enum gpio_mode mode);
enum gpio_result dal_gpio_open_ex(
struct gpio *gpio,
enum gpio_mode mode);
/* Get high or low from the pin */
enum gpio_result dal_gpio_get_value(
const struct gpio *gpio,
uint32_t *value);
/* Set pin high or low */
enum gpio_result dal_gpio_set_value(
const struct gpio *gpio,
uint32_t value);
/* Get current mode */
enum gpio_mode dal_gpio_get_mode(
const struct gpio *gpio);
/* Change mode of the handle */
enum gpio_result dal_gpio_change_mode(
struct gpio *gpio,
enum gpio_mode mode);
/* Get the GPIO id */
enum gpio_id dal_gpio_get_id(
const struct gpio *gpio);
/* Get the GPIO enum */
uint32_t dal_gpio_get_enum(
const struct gpio *gpio);
/* Set the GPIO pin configuration */
enum gpio_result dal_gpio_set_config(
struct gpio *gpio,
const struct gpio_config_data *config_data);
/* Obtain GPIO pin info */
enum gpio_result dal_gpio_get_pin_info(
const struct gpio *gpio,
struct gpio_pin_info *pin_info);
/* Obtain GPIO sync source */
enum sync_source dal_gpio_get_sync_source(
const struct gpio *gpio);
/* Obtain GPIO pin output state (active low or active high) */
enum gpio_pin_output_state dal_gpio_get_output_state(
const struct gpio *gpio);
/* Close the handle */
void dal_gpio_close(
struct gpio *gpio);
#endif

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_GPIO_SERVICE_INTERFACE_H__
#define __DAL_GPIO_SERVICE_INTERFACE_H__
#include "gpio_types.h"
#include "gpio_interface.h"
#include "hw/gpio.h"
struct gpio_service;
struct gpio *dal_gpio_create(
struct gpio_service *service,
enum gpio_id id,
uint32_t en,
enum gpio_pin_output_state output_state);
void dal_gpio_destroy(
struct gpio **ptr);
struct gpio_service *dal_gpio_service_create(
enum dce_version dce_version_major,
enum dce_version dce_version_minor,
struct dc_context *ctx);
struct gpio *dal_gpio_service_create_irq(
struct gpio_service *service,
uint32_t offset,
uint32_t mask);
struct ddc *dal_gpio_create_ddc(
struct gpio_service *service,
uint32_t offset,
uint32_t mask,
struct gpio_ddc_hw_info *info);
void dal_gpio_destroy_ddc(
struct ddc **ddc);
void dal_gpio_service_destroy(
struct gpio_service **ptr);
enum dc_irq_source dal_irq_get_source(
const struct gpio *irq);
enum dc_irq_source dal_irq_get_rx_source(
const struct gpio *irq);
enum gpio_result dal_irq_setup_hpd_filter(
struct gpio *irq,
struct gpio_hpd_config *config);
struct gpio *dal_gpio_create_irq(
struct gpio_service *service,
enum gpio_id id,
uint32_t en);
void dal_gpio_destroy_irq(
struct gpio **ptr);
enum gpio_result dal_ddc_open(
struct ddc *ddc,
enum gpio_mode mode,
enum gpio_ddc_config_type config_type);
enum gpio_result dal_ddc_change_mode(
struct ddc *ddc,
enum gpio_mode mode);
enum gpio_ddc_line dal_ddc_get_line(
const struct ddc *ddc);
enum gpio_result dal_ddc_set_config(
struct ddc *ddc,
enum gpio_ddc_config_type config_type);
void dal_ddc_close(
struct ddc *ddc);
#endif

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_GPIO_TYPES_H__
#define __DAL_GPIO_TYPES_H__
#define BUNDLE_A_MASK 0x00FFF000L
#define BUNDLE_B_MASK 0x00000FFFL
/*
* gpio_result
*
* @brief
* The possible return codes that the GPIO object can return.
* These return codes can be generated
* directly by the GPIO object or from the GPIOPin object.
*/
enum gpio_result {
GPIO_RESULT_OK,
GPIO_RESULT_NULL_HANDLE,
GPIO_RESULT_INVALID_DATA,
GPIO_RESULT_DEVICE_BUSY,
GPIO_RESULT_OPEN_FAILED,
GPIO_RESULT_ALREADY_OPENED,
GPIO_RESULT_NON_SPECIFIC_ERROR
};
/*
* @brief
* Used to identify the specific GPIO device
*
* @notes
* These constants are used as indices in a vector.
* Thus they should start from zero and be contiguous.
*/
enum gpio_id {
GPIO_ID_UNKNOWN = (-1),
GPIO_ID_DDC_DATA,
GPIO_ID_DDC_CLOCK,
GPIO_ID_GENERIC,
GPIO_ID_HPD,
GPIO_ID_GPIO_PAD,
GPIO_ID_VIP_PAD,
GPIO_ID_SYNC,
GPIO_ID_GSL, /* global swap lock */
GPIO_ID_COUNT,
GPIO_ID_MIN = GPIO_ID_DDC_DATA,
GPIO_ID_MAX = GPIO_ID_GSL
};
#define GPIO_ENUM_UNKNOWN \
32
struct gpio_pin_info {
uint32_t offset;
uint32_t offset_y;
uint32_t offset_en;
uint32_t offset_mask;
uint32_t mask;
uint32_t mask_y;
uint32_t mask_en;
uint32_t mask_mask;
};
enum gpio_pin_output_state {
GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW,
GPIO_PIN_OUTPUT_STATE_ACTIVE_HIGH,
GPIO_PIN_OUTPUT_STATE_DEFAULT = GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW
};
enum gpio_generic {
GPIO_GENERIC_UNKNOWN = (-1),
GPIO_GENERIC_A,
GPIO_GENERIC_B,
GPIO_GENERIC_C,
GPIO_GENERIC_D,
GPIO_GENERIC_E,
GPIO_GENERIC_F,
GPIO_GENERIC_G,
GPIO_GENERIC_COUNT,
GPIO_GENERIC_MIN = GPIO_GENERIC_A,
GPIO_GENERIC_MAX = GPIO_GENERIC_B
};
enum gpio_hpd {
GPIO_HPD_UNKNOWN = (-1),
GPIO_HPD_1,
GPIO_HPD_2,
GPIO_HPD_3,
GPIO_HPD_4,
GPIO_HPD_5,
GPIO_HPD_6,
GPIO_HPD_COUNT,
GPIO_HPD_MIN = GPIO_HPD_1,
GPIO_HPD_MAX = GPIO_HPD_6
};
enum gpio_gpio_pad {
GPIO_GPIO_PAD_UNKNOWN = (-1),
GPIO_GPIO_PAD_0,
GPIO_GPIO_PAD_1,
GPIO_GPIO_PAD_2,
GPIO_GPIO_PAD_3,
GPIO_GPIO_PAD_4,
GPIO_GPIO_PAD_5,
GPIO_GPIO_PAD_6,
GPIO_GPIO_PAD_7,
GPIO_GPIO_PAD_8,
GPIO_GPIO_PAD_9,
GPIO_GPIO_PAD_10,
GPIO_GPIO_PAD_11,
GPIO_GPIO_PAD_12,
GPIO_GPIO_PAD_13,
GPIO_GPIO_PAD_14,
GPIO_GPIO_PAD_15,
GPIO_GPIO_PAD_16,
GPIO_GPIO_PAD_17,
GPIO_GPIO_PAD_18,
GPIO_GPIO_PAD_19,
GPIO_GPIO_PAD_20,
GPIO_GPIO_PAD_21,
GPIO_GPIO_PAD_22,
GPIO_GPIO_PAD_23,
GPIO_GPIO_PAD_24,
GPIO_GPIO_PAD_25,
GPIO_GPIO_PAD_26,
GPIO_GPIO_PAD_27,
GPIO_GPIO_PAD_28,
GPIO_GPIO_PAD_29,
GPIO_GPIO_PAD_30,
GPIO_GPIO_PAD_COUNT,
GPIO_GPIO_PAD_MIN = GPIO_GPIO_PAD_0,
GPIO_GPIO_PAD_MAX = GPIO_GPIO_PAD_30
};
enum gpio_vip_pad {
GPIO_VIP_PAD_UNKNOWN = (-1),
/* following never used -
* GPIO_ID_DDC_CLOCK::GPIO_DDC_LINE_VIP_PAD defined instead */
GPIO_VIP_PAD_SCL,
/* following never used -
* GPIO_ID_DDC_DATA::GPIO_DDC_LINE_VIP_PAD defined instead */
GPIO_VIP_PAD_SDA,
GPIO_VIP_PAD_VHAD,
GPIO_VIP_PAD_VPHCTL,
GPIO_VIP_PAD_VIPCLK,
GPIO_VIP_PAD_VID,
GPIO_VIP_PAD_VPCLK0,
GPIO_VIP_PAD_DVALID,
GPIO_VIP_PAD_PSYNC,
GPIO_VIP_PAD_COUNT,
GPIO_VIP_PAD_MIN = GPIO_VIP_PAD_SCL,
GPIO_VIP_PAD_MAX = GPIO_VIP_PAD_PSYNC
};
enum gpio_sync {
GPIO_SYNC_UNKNOWN = (-1),
GPIO_SYNC_HSYNC_A,
GPIO_SYNC_VSYNC_A,
GPIO_SYNC_HSYNC_B,
GPIO_SYNC_VSYNC_B,
GPIO_SYNC_COUNT,
GPIO_SYNC_MIN = GPIO_SYNC_HSYNC_A,
GPIO_SYNC_MAX = GPIO_SYNC_VSYNC_B
};
enum gpio_gsl {
GPIO_GSL_UNKNOWN = (-1),
GPIO_GSL_GENLOCK_CLOCK,
GPIO_GSL_GENLOCK_VSYNC,
GPIO_GSL_SWAPLOCK_A,
GPIO_GSL_SWAPLOCK_B,
GPIO_GSL_COUNT,
GPIO_GSL_MIN = GPIO_GSL_GENLOCK_CLOCK,
GPIO_GSL_MAX = GPIO_GSL_SWAPLOCK_B
};
/*
* @brief
* Unique Id for DDC handle.
* Values are meaningful (used as indexes to array)
*/
enum gpio_ddc_line {
GPIO_DDC_LINE_UNKNOWN = (-1),
GPIO_DDC_LINE_DDC1,
GPIO_DDC_LINE_DDC2,
GPIO_DDC_LINE_DDC3,
GPIO_DDC_LINE_DDC4,
GPIO_DDC_LINE_DDC5,
GPIO_DDC_LINE_DDC6,
GPIO_DDC_LINE_DDC_VGA,
GPIO_DDC_LINE_VIP_PAD,
GPIO_DDC_LINE_I2C_PAD = GPIO_DDC_LINE_VIP_PAD,
GPIO_DDC_LINE_COUNT,
GPIO_DDC_LINE_MIN = GPIO_DDC_LINE_DDC1,
GPIO_DDC_LINE_MAX = GPIO_DDC_LINE_I2C_PAD
};
/*
* @brief
* Identifies the mode of operation to open a GPIO device.
* A GPIO device (pin) can be programmed in only one of these modes at a time.
*/
enum gpio_mode {
GPIO_MODE_UNKNOWN = (-1),
GPIO_MODE_INPUT,
GPIO_MODE_OUTPUT,
GPIO_MODE_FAST_OUTPUT,
GPIO_MODE_HARDWARE,
GPIO_MODE_INTERRUPT
};
/*
* @brief
* Identifies the source of the signal when GPIO is in HW mode.
* get_signal_source() will return GPIO_SYGNAL_SOURCE__UNKNOWN
* when one of the following holds:
* 1. GPIO is input GPIO
* 2. GPIO is not opened in HW mode
* 3. GPIO does not have fixed signal source
* (like DC_GenericA have mux instead fixed)
*/
enum gpio_signal_source {
GPIO_SIGNAL_SOURCE_UNKNOWN = (-1),
GPIO_SIGNAL_SOURCE_DACA_STEREO_SYNC,
GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC,
GPIO_SIGNAL_SOURCE_DACB_STEREO_SYNC,
GPIO_SIGNAL_SOURCE_DACA_HSYNC,
GPIO_SIGNAL_SOURCE_DACB_HSYNC,
GPIO_SIGNAL_SOURCE_DACA_VSYNC,
GPIO_SIGNAL_SOURCE_DACB_VSYNC,
};
enum gpio_stereo_source {
GPIO_STEREO_SOURCE_UNKNOWN = (-1),
GPIO_STEREO_SOURCE_D1,
GPIO_STEREO_SOURCE_D2,
GPIO_STEREO_SOURCE_D3,
GPIO_STEREO_SOURCE_D4,
GPIO_STEREO_SOURCE_D5,
GPIO_STEREO_SOURCE_D6
};
/*
* GPIO config
*/
enum gpio_config_type {
GPIO_CONFIG_TYPE_NONE,
GPIO_CONFIG_TYPE_DDC,
GPIO_CONFIG_TYPE_HPD,
GPIO_CONFIG_TYPE_GENERIC_MUX,
GPIO_CONFIG_TYPE_GSL_MUX,
GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE
};
/* DDC configuration */
enum gpio_ddc_config_type {
GPIO_DDC_CONFIG_TYPE_MODE_AUX,
GPIO_DDC_CONFIG_TYPE_MODE_I2C,
GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT,
GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT,
GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING
};
struct gpio_ddc_config {
enum gpio_ddc_config_type type;
bool data_en_bit_present;
bool clock_en_bit_present;
};
/* HPD configuration */
struct gpio_hpd_config {
uint32_t delay_on_connect; /* milliseconds */
uint32_t delay_on_disconnect; /* milliseconds */
};
struct gpio_generic_mux_config {
bool enable_output_from_mux;
enum gpio_signal_source mux_select;
enum gpio_stereo_source stereo_select;
};
enum gpio_gsl_mux_config_type {
GPIO_GSL_MUX_CONFIG_TYPE_DISABLE,
GPIO_GSL_MUX_CONFIG_TYPE_TIMING_SYNC,
GPIO_GSL_MUX_CONFIG_TYPE_FLIP_SYNC
};
struct gpio_gsl_mux_config {
enum gpio_gsl_mux_config_type type;
/* Actually sync_source type,
* however we want to avoid inter-component includes here */
uint32_t gsl_group;
};
struct gpio_config_data {
enum gpio_config_type type;
union {
struct gpio_ddc_config ddc;
struct gpio_hpd_config hpd;
struct gpio_generic_mux_config generic_mux;
struct gpio_gsl_mux_config gsl_mux;
} config;
};
#endif

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_GRPH_OBJECT_CTRL_DEFS_H__
#define __DAL_GRPH_OBJECT_CTRL_DEFS_H__
#include "grph_object_defs.h"
/*
* #####################################################
* #####################################################
*
* These defines shared between asic_control/bios_parser and other
* DAL components
*
* #####################################################
* #####################################################
*/
enum display_output_bit_depth {
PANEL_UNDEFINE = 0,
PANEL_6BIT_COLOR = 1,
PANEL_8BIT_COLOR = 2,
PANEL_10BIT_COLOR = 3,
PANEL_12BIT_COLOR = 4,
PANEL_16BIT_COLOR = 5,
};
/* Device type as abstracted by ATOM BIOS */
enum dal_device_type {
DEVICE_TYPE_UNKNOWN = 0,
DEVICE_TYPE_LCD,
DEVICE_TYPE_CRT,
DEVICE_TYPE_DFP,
DEVICE_TYPE_CV,
DEVICE_TYPE_TV,
DEVICE_TYPE_CF,
DEVICE_TYPE_WIRELESS
};
/* Device ID as abstracted by ATOM BIOS */
struct device_id {
enum dal_device_type device_type:16;
uint32_t enum_id:16; /* 1 based enum */
};
struct graphics_object_i2c_info {
struct gpio_info {
uint32_t clk_mask_register_index;
uint32_t clk_en_register_index;
uint32_t clk_y_register_index;
uint32_t clk_a_register_index;
uint32_t data_mask_register_index;
uint32_t data_en_register_index;
uint32_t data_y_register_index;
uint32_t data_a_register_index;
uint32_t clk_mask_shift;
uint32_t clk_en_shift;
uint32_t clk_y_shift;
uint32_t clk_a_shift;
uint32_t data_mask_shift;
uint32_t data_en_shift;
uint32_t data_y_shift;
uint32_t data_a_shift;
} gpio_info;
bool i2c_hw_assist;
uint32_t i2c_line;
uint32_t i2c_engine_id;
uint32_t i2c_slave_address;
};
struct graphics_object_hpd_info {
uint8_t hpd_int_gpio_uid;
uint8_t hpd_active;
};
struct connector_device_tag_info {
uint32_t acpi_device;
struct device_id dev_id;
};
struct device_timing {
struct misc_info {
uint32_t HORIZONTAL_CUT_OFF:1;
/* 0=Active High, 1=Active Low */
uint32_t H_SYNC_POLARITY:1;
/* 0=Active High, 1=Active Low */
uint32_t V_SYNC_POLARITY:1;
uint32_t VERTICAL_CUT_OFF:1;
uint32_t H_REPLICATION_BY2:1;
uint32_t V_REPLICATION_BY2:1;
uint32_t COMPOSITE_SYNC:1;
uint32_t INTERLACE:1;
uint32_t DOUBLE_CLOCK:1;
uint32_t RGB888:1;
uint32_t GREY_LEVEL:2;
uint32_t SPATIAL:1;
uint32_t TEMPORAL:1;
uint32_t API_ENABLED:1;
} misc_info;
uint32_t pixel_clk; /* in KHz */
uint32_t horizontal_addressable;
uint32_t horizontal_blanking_time;
uint32_t vertical_addressable;
uint32_t vertical_blanking_time;
uint32_t horizontal_sync_offset;
uint32_t horizontal_sync_width;
uint32_t vertical_sync_offset;
uint32_t vertical_sync_width;
uint32_t horizontal_border;
uint32_t vertical_border;
};
struct supported_refresh_rate {
uint32_t REFRESH_RATE_30HZ:1;
uint32_t REFRESH_RATE_40HZ:1;
uint32_t REFRESH_RATE_48HZ:1;
uint32_t REFRESH_RATE_50HZ:1;
uint32_t REFRESH_RATE_60HZ:1;
};
struct embedded_panel_info {
struct device_timing lcd_timing;
uint32_t ss_id;
struct supported_refresh_rate supported_rr;
uint32_t drr_enabled;
uint32_t min_drr_refresh_rate;
bool realtek_eDPToLVDS;
};
struct firmware_info {
struct pll_info {
uint32_t crystal_frequency; /* in KHz */
uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */
uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */
uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */
uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */
} pll_info;
struct firmware_feature {
uint32_t memory_clk_ss_percentage;
uint32_t engine_clk_ss_percentage;
} feature;
uint32_t default_display_engine_pll_frequency; /* in KHz */
uint32_t external_clock_source_frequency_for_dp; /* in KHz */
uint32_t smu_gpu_pll_output_freq; /* in KHz */
uint8_t min_allowed_bl_level;
uint8_t remote_display_config;
uint32_t default_memory_clk; /* in KHz */
uint32_t default_engine_clk; /* in KHz */
uint32_t dp_phy_ref_clk; /* in KHz - DCE12 only */
uint32_t i2c_engine_ref_clk; /* in KHz - DCE12 only */
};
struct step_and_delay_info {
uint32_t step;
uint32_t delay;
uint32_t recommended_ref_div;
};
struct spread_spectrum_info {
struct spread_spectrum_type {
bool CENTER_MODE:1;
bool EXTERNAL:1;
bool STEP_AND_DELAY_INFO:1;
} type;
/* in unit of 0.01% (spreadPercentageDivider = 100),
otherwise in 0.001% units (spreadPercentageDivider = 1000); */
uint32_t spread_spectrum_percentage;
uint32_t spread_percentage_divider; /* 100 or 1000 */
uint32_t spread_spectrum_range; /* modulation freq (HZ)*/
union {
struct step_and_delay_info step_and_delay_info;
/* For mem/engine/uvd, Clock Out frequence (VCO ),
in unit of kHz. For TMDS/HDMI/LVDS, it is pixel clock,
for DP, it is link clock ( 270000 or 162000 ) */
uint32_t target_clock_range; /* in KHz */
};
};
struct graphics_object_encoder_cap_info {
uint32_t dp_hbr2_cap:1;
uint32_t dp_hbr2_validated:1;
/*
* TODO: added MST and HDMI 6G capable flags
*/
uint32_t reserved:15;
};
struct din_connector_info {
uint32_t gpio_id;
bool gpio_tv_active_state;
};
/* Invalid channel mapping */
enum { INVALID_DDI_CHANNEL_MAPPING = 0x0 };
/**
* DDI PHY channel mapping reflecting XBAR setting
*/
union ddi_channel_mapping {
struct mapping {
uint8_t lane0:2; /* Mapping for lane 0 */
uint8_t lane1:2; /* Mapping for lane 1 */
uint8_t lane2:2; /* Mapping for lane 2 */
uint8_t lane3:2; /* Mapping for lane 3 */
} mapping;
uint8_t raw;
};
/**
* Transmitter output configuration description
*/
struct transmitter_configuration_info {
/* DDI PHY ID for the transmitter */
enum transmitter transmitter_phy_id;
/* DDI PHY channel mapping reflecting crossbar setting */
union ddi_channel_mapping output_channel_mapping;
};
struct transmitter_configuration {
/* Configuration for the primary transmitter */
struct transmitter_configuration_info primary_transmitter_config;
/* Secondary transmitter configuration for Dual-link DVI */
struct transmitter_configuration_info secondary_transmitter_config;
};
/* These size should be sufficient to store info coming from BIOS */
#define NUMBER_OF_UCHAR_FOR_GUID 16
#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
#define NUMBER_OF_CSR_M3_ARB 10
#define NUMBER_OF_DISP_CLK_VOLTAGE 4
#define NUMBER_OF_AVAILABLE_SCLK 5
/* V6 */
struct integrated_info {
struct clock_voltage_caps {
/* The Voltage Index indicated by FUSE, same voltage index
shared with SCLK DPM fuse table */
uint32_t voltage_index;
/* Maximum clock supported with specified voltage index */
uint32_t max_supported_clk; /* in KHz */
} disp_clk_voltage[NUMBER_OF_DISP_CLK_VOLTAGE];
struct display_connection_info {
struct external_display_path {
/* A bit vector to show what devices are supported */
uint32_t device_tag;
/* 16bit device ACPI id. */
uint32_t device_acpi_enum;
/* A physical connector for displays to plug in,
using object connector definitions */
struct graphics_object_id device_connector_id;
/* An index into external AUX/DDC channel LUT */
uint8_t ext_aux_ddc_lut_index;
/* An index into external HPD pin LUT */
uint8_t ext_hpd_pin_lut_index;
/* external encoder object id */
struct graphics_object_id ext_encoder_obj_id;
/* XBAR mapping of the PHY channels */
union ddi_channel_mapping channel_mapping;
} path[MAX_NUMBER_OF_EXT_DISPLAY_PATH];
uint8_t gu_id[NUMBER_OF_UCHAR_FOR_GUID];
uint8_t checksum;
} ext_disp_conn_info; /* exiting long long time */
struct available_s_clk_list {
/* Maximum clock supported with specified voltage index */
uint32_t supported_s_clk; /* in KHz */
/* The Voltage Index indicated by FUSE for specified SCLK */
uint32_t voltage_index;
/* The Voltage ID indicated by FUSE for specified SCLK */
uint32_t voltage_id;
} avail_s_clk[NUMBER_OF_AVAILABLE_SCLK];
uint8_t memory_type;
uint8_t ma_channel_number;
uint32_t boot_up_engine_clock; /* in KHz */
uint32_t dentist_vco_freq; /* in KHz */
uint32_t boot_up_uma_clock; /* in KHz */
uint32_t boot_up_req_display_vector;
uint32_t other_display_misc;
uint32_t gpu_cap_info;
uint32_t sb_mmio_base_addr;
uint32_t system_config;
uint32_t cpu_cap_info;
uint32_t max_nb_voltage;
uint32_t min_nb_voltage;
uint32_t boot_up_nb_voltage;
uint32_t ext_disp_conn_info_offset;
uint32_t csr_m3_arb_cntl_default[NUMBER_OF_CSR_M3_ARB];
uint32_t csr_m3_arb_cntl_uvd[NUMBER_OF_CSR_M3_ARB];
uint32_t csr_m3_arb_cntl_fs3d[NUMBER_OF_CSR_M3_ARB];
uint32_t gmc_restore_reset_time;
uint32_t minimum_n_clk;
uint32_t idle_n_clk;
uint32_t ddr_dll_power_up_time;
uint32_t ddr_pll_power_up_time;
/* start for V6 */
uint32_t pcie_clk_ss_type;
uint32_t lvds_ss_percentage;
uint32_t lvds_sspread_rate_in_10hz;
uint32_t hdmi_ss_percentage;
uint32_t hdmi_sspread_rate_in_10hz;
uint32_t dvi_ss_percentage;
uint32_t dvi_sspread_rate_in_10_hz;
uint32_t sclk_dpm_boost_margin;
uint32_t sclk_dpm_throttle_margin;
uint32_t sclk_dpm_tdp_limit_pg;
uint32_t sclk_dpm_tdp_limit_boost;
uint32_t boost_engine_clock;
uint32_t boost_vid_2bit;
uint32_t enable_boost;
uint32_t gnb_tdp_limit;
/* Start from V7 */
uint32_t max_lvds_pclk_freq_in_single_link;
uint32_t lvds_misc;
uint32_t lvds_pwr_on_seq_dig_on_to_de_in_4ms;
uint32_t lvds_pwr_on_seq_de_to_vary_bl_in_4ms;
uint32_t lvds_pwr_off_seq_vary_bl_to_de_in4ms;
uint32_t lvds_pwr_off_seq_de_to_dig_on_in4ms;
uint32_t lvds_off_to_on_delay_in_4ms;
uint32_t lvds_pwr_on_seq_vary_bl_to_blon_in_4ms;
uint32_t lvds_pwr_off_seq_blon_to_vary_bl_in_4ms;
uint32_t lvds_reserved1;
uint32_t lvds_bit_depth_control_val;
};
/**
* Power source ids.
*/
enum power_source {
POWER_SOURCE_AC = 0,
POWER_SOURCE_DC,
POWER_SOURCE_LIMITED_POWER,
POWER_SOURCE_LIMITED_POWER_2,
POWER_SOURCE_MAX
};
struct bios_event_info {
uint32_t thermal_state;
uint32_t backlight_level;
enum power_source powerSource;
bool has_thermal_state_changed;
bool has_power_source_changed;
bool has_forced_mode_changed;
bool forced_mode;
bool backlight_changed;
};
enum {
HDMI_PIXEL_CLOCK_IN_KHZ_297 = 297000,
TMDS_PIXEL_CLOCK_IN_KHZ_165 = 165000
};
/*
* DFS-bypass flag
*/
/* Copy of SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS from atombios.h */
enum {
DFS_BYPASS_ENABLE = 0x10
};
enum {
INVALID_BACKLIGHT = -1
};
struct panel_backlight_boundaries {
uint32_t min_signal_level;
uint32_t max_signal_level;
};
#endif

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drivers/gpu/drm/amd/display/include/grph_object_defs.h Normal file
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_GRPH_OBJECT_DEFS_H__
#define __DAL_GRPH_OBJECT_DEFS_H__
#include "grph_object_id.h"
/* ********************************************************************
* ********************************************************************
*
* These defines shared between All Graphics Objects
*
* ********************************************************************
* ********************************************************************
*/
/* HPD unit id - HW direct translation */
enum hpd_source_id {
HPD_SOURCEID1 = 0,
HPD_SOURCEID2,
HPD_SOURCEID3,
HPD_SOURCEID4,
HPD_SOURCEID5,
HPD_SOURCEID6,
HPD_SOURCEID_COUNT,
HPD_SOURCEID_UNKNOWN
};
/* DDC unit id - HW direct translation */
enum channel_id {
CHANNEL_ID_UNKNOWN = 0,
CHANNEL_ID_DDC1,
CHANNEL_ID_DDC2,
CHANNEL_ID_DDC3,
CHANNEL_ID_DDC4,
CHANNEL_ID_DDC5,
CHANNEL_ID_DDC6,
CHANNEL_ID_DDC_VGA,
CHANNEL_ID_I2C_PAD,
CHANNEL_ID_COUNT
};
#define DECODE_CHANNEL_ID(ch_id) \
(ch_id) == CHANNEL_ID_DDC1 ? "CHANNEL_ID_DDC1" : \
(ch_id) == CHANNEL_ID_DDC2 ? "CHANNEL_ID_DDC2" : \
(ch_id) == CHANNEL_ID_DDC3 ? "CHANNEL_ID_DDC3" : \
(ch_id) == CHANNEL_ID_DDC4 ? "CHANNEL_ID_DDC4" : \
(ch_id) == CHANNEL_ID_DDC5 ? "CHANNEL_ID_DDC5" : \
(ch_id) == CHANNEL_ID_DDC6 ? "CHANNEL_ID_DDC6" : \
(ch_id) == CHANNEL_ID_DDC_VGA ? "CHANNEL_ID_DDC_VGA" : \
(ch_id) == CHANNEL_ID_I2C_PAD ? "CHANNEL_ID_I2C_PAD" : "Invalid"
enum transmitter {
TRANSMITTER_UNKNOWN = (-1L),
TRANSMITTER_UNIPHY_A,
TRANSMITTER_UNIPHY_B,
TRANSMITTER_UNIPHY_C,
TRANSMITTER_UNIPHY_D,
TRANSMITTER_UNIPHY_E,
TRANSMITTER_UNIPHY_F,
TRANSMITTER_NUTMEG_CRT,
TRANSMITTER_TRAVIS_CRT,
TRANSMITTER_TRAVIS_LCD,
TRANSMITTER_UNIPHY_G,
TRANSMITTER_COUNT
};
/* Generic source of the synchronisation input/output signal */
/* Can be used for flow control, stereo sync, timing sync, frame sync, etc */
enum sync_source {
SYNC_SOURCE_NONE = 0,
/* Source based on controllers */
SYNC_SOURCE_CONTROLLER0,
SYNC_SOURCE_CONTROLLER1,
SYNC_SOURCE_CONTROLLER2,
SYNC_SOURCE_CONTROLLER3,
SYNC_SOURCE_CONTROLLER4,
SYNC_SOURCE_CONTROLLER5,
/* Source based on GSL group */
SYNC_SOURCE_GSL_GROUP0,
SYNC_SOURCE_GSL_GROUP1,
SYNC_SOURCE_GSL_GROUP2,
/* Source based on GSL IOs */
/* These IOs normally used as GSL input/output */
SYNC_SOURCE_GSL_IO_FIRST,
SYNC_SOURCE_GSL_IO_GENLOCK_CLOCK = SYNC_SOURCE_GSL_IO_FIRST,
SYNC_SOURCE_GSL_IO_GENLOCK_VSYNC,
SYNC_SOURCE_GSL_IO_SWAPLOCK_A,
SYNC_SOURCE_GSL_IO_SWAPLOCK_B,
SYNC_SOURCE_GSL_IO_LAST = SYNC_SOURCE_GSL_IO_SWAPLOCK_B,
/* Source based on regular IOs */
SYNC_SOURCE_IO_FIRST,
SYNC_SOURCE_IO_GENERIC_A = SYNC_SOURCE_IO_FIRST,
SYNC_SOURCE_IO_GENERIC_B,
SYNC_SOURCE_IO_GENERIC_C,
SYNC_SOURCE_IO_GENERIC_D,
SYNC_SOURCE_IO_GENERIC_E,
SYNC_SOURCE_IO_GENERIC_F,
SYNC_SOURCE_IO_HPD1,
SYNC_SOURCE_IO_HPD2,
SYNC_SOURCE_IO_HSYNC_A,
SYNC_SOURCE_IO_VSYNC_A,
SYNC_SOURCE_IO_HSYNC_B,
SYNC_SOURCE_IO_VSYNC_B,
SYNC_SOURCE_IO_LAST = SYNC_SOURCE_IO_VSYNC_B,
/* Misc. flow control sources */
SYNC_SOURCE_DUAL_GPU_PIN
};
#endif

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_GRPH_OBJECT_ID_H__
#define __DAL_GRPH_OBJECT_ID_H__
/* Types of graphics objects */
enum object_type {
OBJECT_TYPE_UNKNOWN = 0,
/* Direct ATOM BIOS translation */
OBJECT_TYPE_GPU,
OBJECT_TYPE_ENCODER,
OBJECT_TYPE_CONNECTOR,
OBJECT_TYPE_ROUTER,
OBJECT_TYPE_GENERIC,
/* Driver specific */
OBJECT_TYPE_AUDIO,
OBJECT_TYPE_CONTROLLER,
OBJECT_TYPE_CLOCK_SOURCE,
OBJECT_TYPE_ENGINE,
OBJECT_TYPE_COUNT
};
/* Enumeration inside one type of graphics objects */
enum object_enum_id {
ENUM_ID_UNKNOWN = 0,
ENUM_ID_1,
ENUM_ID_2,
ENUM_ID_3,
ENUM_ID_4,
ENUM_ID_5,
ENUM_ID_6,
ENUM_ID_7,
ENUM_ID_COUNT
};
/* Generic object ids */
enum generic_id {
GENERIC_ID_UNKNOWN = 0,
GENERIC_ID_MXM_OPM,
GENERIC_ID_GLSYNC,
GENERIC_ID_STEREO,
GENERIC_ID_COUNT
};
/* Controller object ids */
enum controller_id {
CONTROLLER_ID_UNDEFINED = 0,
CONTROLLER_ID_D0,
CONTROLLER_ID_D1,
CONTROLLER_ID_D2,
CONTROLLER_ID_D3,
CONTROLLER_ID_D4,
CONTROLLER_ID_D5,
CONTROLLER_ID_UNDERLAY0,
CONTROLLER_ID_MAX = CONTROLLER_ID_UNDERLAY0
};
#define IS_UNDERLAY_CONTROLLER(ctrlr_id) (ctrlr_id >= CONTROLLER_ID_UNDERLAY0)
/*
* ClockSource object ids.
* We maintain the order matching (more or less) ATOM BIOS
* to improve optimized acquire
*/
enum clock_source_id {
CLOCK_SOURCE_ID_UNDEFINED = 0,
CLOCK_SOURCE_ID_PLL0,
CLOCK_SOURCE_ID_PLL1,
CLOCK_SOURCE_ID_PLL2,
CLOCK_SOURCE_ID_EXTERNAL, /* ID (Phy) ref. clk. for DP */
CLOCK_SOURCE_ID_DCPLL,
CLOCK_SOURCE_ID_DFS, /* DENTIST */
CLOCK_SOURCE_ID_VCE, /* VCE does not need a real PLL */
/* Used to distinguish between programming pixel clock and ID (Phy) clock */
CLOCK_SOURCE_ID_DP_DTO,
CLOCK_SOURCE_COMBO_PHY_PLL0, /*combo PHY PLL defines (DC 11.2 and up)*/
CLOCK_SOURCE_COMBO_PHY_PLL1,
CLOCK_SOURCE_COMBO_PHY_PLL2,
CLOCK_SOURCE_COMBO_PHY_PLL3,
CLOCK_SOURCE_COMBO_PHY_PLL4,
CLOCK_SOURCE_COMBO_PHY_PLL5,
CLOCK_SOURCE_COMBO_DISPLAY_PLL0
};
/* Encoder object ids */
enum encoder_id {
ENCODER_ID_UNKNOWN = 0,
/* Radeon Class Display Hardware */
ENCODER_ID_INTERNAL_LVDS,
ENCODER_ID_INTERNAL_TMDS1,
ENCODER_ID_INTERNAL_TMDS2,
ENCODER_ID_INTERNAL_DAC1,
ENCODER_ID_INTERNAL_DAC2, /* TV/CV DAC */
/* External Third Party Encoders */
ENCODER_ID_INTERNAL_LVTM1, /* not used for Radeon */
ENCODER_ID_INTERNAL_HDMI,
/* Kaledisope (KLDSCP) Class Display Hardware */
ENCODER_ID_INTERNAL_KLDSCP_TMDS1,
ENCODER_ID_INTERNAL_KLDSCP_DAC1,
ENCODER_ID_INTERNAL_KLDSCP_DAC2, /* Shared with CV/TV and CRT */
/* External TMDS (dual link) */
ENCODER_ID_EXTERNAL_MVPU_FPGA, /* MVPU FPGA chip */
ENCODER_ID_INTERNAL_DDI,
ENCODER_ID_INTERNAL_UNIPHY,
ENCODER_ID_INTERNAL_KLDSCP_LVTMA,
ENCODER_ID_INTERNAL_UNIPHY1,
ENCODER_ID_INTERNAL_UNIPHY2,
ENCODER_ID_EXTERNAL_NUTMEG,
ENCODER_ID_EXTERNAL_TRAVIS,
ENCODER_ID_INTERNAL_WIRELESS, /* Internal wireless display encoder */
ENCODER_ID_INTERNAL_UNIPHY3,
ENCODER_ID_INTERNAL_VIRTUAL,
};
/* Connector object ids */
enum connector_id {
CONNECTOR_ID_UNKNOWN = 0,
CONNECTOR_ID_SINGLE_LINK_DVII = 1,
CONNECTOR_ID_DUAL_LINK_DVII = 2,
CONNECTOR_ID_SINGLE_LINK_DVID = 3,
CONNECTOR_ID_DUAL_LINK_DVID = 4,
CONNECTOR_ID_VGA = 5,
CONNECTOR_ID_HDMI_TYPE_A = 12,
CONNECTOR_ID_LVDS = 14,
CONNECTOR_ID_PCIE = 16,
CONNECTOR_ID_HARDCODE_DVI = 18,
CONNECTOR_ID_DISPLAY_PORT = 19,
CONNECTOR_ID_EDP = 20,
CONNECTOR_ID_MXM = 21,
CONNECTOR_ID_WIRELESS = 22,
CONNECTOR_ID_MIRACAST = 23,
CONNECTOR_ID_VIRTUAL = 100
};
/* Audio object ids */
enum audio_id {
AUDIO_ID_UNKNOWN = 0,
AUDIO_ID_INTERNAL_AZALIA
};
/* Engine object ids */
enum engine_id {
ENGINE_ID_DIGA,
ENGINE_ID_DIGB,
ENGINE_ID_DIGC,
ENGINE_ID_DIGD,
ENGINE_ID_DIGE,
ENGINE_ID_DIGF,
ENGINE_ID_DIGG,
ENGINE_ID_DACA,
ENGINE_ID_DACB,
ENGINE_ID_VCE, /* wireless display pseudo-encoder */
ENGINE_ID_VIRTUAL,
ENGINE_ID_COUNT,
ENGINE_ID_UNKNOWN = (-1L)
};
enum transmitter_color_depth {
TRANSMITTER_COLOR_DEPTH_24 = 0, /* 8 bits */
TRANSMITTER_COLOR_DEPTH_30, /* 10 bits */
TRANSMITTER_COLOR_DEPTH_36, /* 12 bits */
TRANSMITTER_COLOR_DEPTH_48 /* 16 bits */
};
/*
*****************************************************************************
* graphics_object_id struct
*
* graphics_object_id is a very simple struct wrapping 32bit Graphics
* Object identication
*
* This struct should stay very simple
* No dependencies at all (no includes)
* No debug messages or asserts
* No #ifndef and preprocessor directives
* No grow in space (no more data member)
*****************************************************************************
*/
struct graphics_object_id {
uint32_t id:8;
uint32_t enum_id:4;
uint32_t type:4;
uint32_t reserved:16; /* for padding. total size should be u32 */
};
/* some simple functions for convenient graphics_object_id handle */
static inline struct graphics_object_id dal_graphics_object_id_init(
uint32_t id,
enum object_enum_id enum_id,
enum object_type type)
{
struct graphics_object_id result = {
id, enum_id, type, 0
};
return result;
}
bool dal_graphics_object_id_is_valid(
struct graphics_object_id id);
bool dal_graphics_object_id_is_equal(
struct graphics_object_id id1,
struct graphics_object_id id2);
uint32_t dal_graphics_object_id_to_uint(
struct graphics_object_id id);
enum controller_id dal_graphics_object_id_get_controller_id(
struct graphics_object_id id);
enum clock_source_id dal_graphics_object_id_get_clock_source_id(
struct graphics_object_id id);
enum encoder_id dal_graphics_object_id_get_encoder_id(
struct graphics_object_id id);
enum connector_id dal_graphics_object_id_get_connector_id(
struct graphics_object_id id);
enum audio_id dal_graphics_object_id_get_audio_id(
struct graphics_object_id id);
enum engine_id dal_graphics_object_id_get_engine_id(
struct graphics_object_id id);
#endif

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_HW_SEQUENCER_TYPES_H__
#define __DAL_HW_SEQUENCER_TYPES_H__
#include "signal_types.h"
#include "grph_object_defs.h"
#include "link_service_types.h"
/* define the structure of Dynamic Refresh Mode */
struct drr_params {
/* defines the minimum possible vertical dimension of display timing
* for CRTC as supported by the panel */
uint32_t vertical_total_min;
/* defines the maximum possible vertical dimension of display timing
* for CRTC as supported by the panel */
uint32_t vertical_total_max;
};
/* CRTC timing structure */
struct hw_crtc_timing {
uint32_t h_total;
uint32_t h_addressable;
uint32_t h_overscan_left;
uint32_t h_overscan_right;
uint32_t h_sync_start;
uint32_t h_sync_width;
uint32_t v_total;
uint32_t v_addressable;
uint32_t v_overscan_top;
uint32_t v_overscan_bottom;
uint32_t v_sync_start;
uint32_t v_sync_width;
/* in KHz */
uint32_t pixel_clock;
struct {
uint32_t INTERLACED:1;
uint32_t DOUBLESCAN:1;
uint32_t PIXEL_REPETITION:4; /* 1...10 */
uint32_t HSYNC_POSITIVE_POLARITY:1;
uint32_t VSYNC_POSITIVE_POLARITY:1;
/* frame should be packed for 3D
* (currently this refers to HDMI 1.4a FramePacking format */
uint32_t HORZ_COUNT_BY_TWO:1;
uint32_t PACK_3D_FRAME:1;
/* 0 - left eye polarity, 1 - right eye polarity */
uint32_t RIGHT_EYE_3D_POLARITY:1;
/* DVI-DL High-Color mode */
uint32_t HIGH_COLOR_DL_MODE:1;
uint32_t Y_ONLY:1;
/* HDMI 2.0 - Support scrambling for TMDS character
* rates less than or equal to 340Mcsc */
uint32_t LTE_340MCSC_SCRAMBLE:1;
} flags;
};
/* TODO hw_info_frame and hw_info_packet structures are same as in encoder
* merge it*/
struct hw_info_packet {
bool valid;
uint8_t hb0;
uint8_t hb1;
uint8_t hb2;
uint8_t hb3;
uint8_t sb[28];
};
struct hw_info_frame {
/* Auxiliary Video Information */
struct hw_info_packet avi_info_packet;
struct hw_info_packet gamut_packet;
struct hw_info_packet vendor_info_packet;
/* Source Product Description */
struct hw_info_packet spd_packet;
/* Video Stream Configuration */
struct hw_info_packet vsc_packet;
};
#endif

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_I2CAUX_INTERFACE_H__
#define __DAL_I2CAUX_INTERFACE_H__
#include "gpio_service_interface.h"
#define DEFAULT_AUX_MAX_DATA_SIZE 16
#define AUX_MAX_DEFER_WRITE_RETRY 20
struct aux_payload {
/* set following flag to read/write I2C data,
* reset it to read/write DPCD data */
bool i2c_over_aux;
/* set following flag to write data,
* reset it to read data */
bool write;
uint32_t address;
uint8_t length;
uint8_t *data;
};
struct aux_command {
struct aux_payload *payloads;
uint8_t number_of_payloads;
/* expressed in milliseconds
* zero means "use default value" */
uint32_t defer_delay;
/* zero means "use default value" */
uint32_t max_defer_write_retry;
};
union aux_config {
struct {
uint32_t ALLOW_AUX_WHEN_HPD_LOW:1;
} bits;
uint32_t raw;
};
struct i2caux;
struct i2caux *dal_i2caux_create(
struct dc_context *ctx);
bool dal_i2caux_submit_i2c_command(
struct i2caux *i2caux,
struct ddc *ddc,
struct i2c_command *cmd);
bool dal_i2caux_submit_aux_command(
struct i2caux *i2caux,
struct ddc *ddc,
struct aux_command *cmd);
void dal_i2caux_configure_aux(
struct i2caux *i2caux,
struct ddc *ddc,
union aux_config cfg);
void dal_i2caux_destroy(
struct i2caux **ptr);
#endif

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drivers/gpu/drm/amd/display/include/irq_interface.h Normal file
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_IRQ_INTERFACE_H__
#define __DAL_IRQ_INTERFACE_H__
#include "gpio_types.h"
#endif

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drivers/gpu/drm/amd/display/include/irq_service_interface.h Normal file
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_IRQ_SERVICE_INTERFACE_H__
#define __DAL_IRQ_SERVICE_INTERFACE_H__
struct irq_service_init_data {
struct dc_context *ctx;
};
struct irq_service;
void dal_irq_service_destroy(struct irq_service **irq_service);
bool dal_irq_service_set(
struct irq_service *irq_service,
enum dc_irq_source source,
bool enable);
bool dal_irq_service_ack(
struct irq_service *irq_service,
enum dc_irq_source source);
enum dc_irq_source dal_irq_service_to_irq_source(
struct irq_service *irq_service,
uint32_t src_id,
uint32_t ext_id);
#endif

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_LINK_SERVICE_TYPES_H__
#define __DAL_LINK_SERVICE_TYPES_H__
#include "grph_object_id.h"
#include "dpcd_defs.h"
#include "dal_types.h"
#include "irq_types.h"
/*struct mst_mgr_callback_object;*/
struct ddc;
struct irq_manager;
enum {
MAX_CONTROLLER_NUM = 6
};
enum link_service_type {
LINK_SERVICE_TYPE_LEGACY = 0,
LINK_SERVICE_TYPE_DP_SST,
LINK_SERVICE_TYPE_DP_MST,
LINK_SERVICE_TYPE_MAX
};
enum dpcd_value_mask {
DPCD_VALUE_MASK_MAX_LANE_COUNT_LANE_COUNT = 0x1F,
DPCD_VALUE_MASK_MAX_LANE_COUNT_TPS3_SUPPORTED = 0x40,
DPCD_VALUE_MASK_MAX_LANE_COUNT_ENHANCED_FRAME_EN = 0x80,
DPCD_VALUE_MASK_MAX_DOWNSPREAD = 0x01,
DPCD_VALUE_MASK_LANE_ALIGN_STATUS_INTERLANE_ALIGN_DONE = 0x01
};
enum dp_power_state {
DP_POWER_STATE_D0 = 1,
DP_POWER_STATE_D3
};
enum dpcd_downstream_port_types {
DPCD_DOWNSTREAM_DP,
DPCD_DOWNSTREAM_VGA,
DPCD_DOWNSTREAM_DVI_HDMI,
/* has no EDID (TV, CV) */
DPCD_DOWNSTREAM_NON_DDC
};
enum edp_revision {
/* eDP version 1.1 or lower */
EDP_REVISION_11 = 0x00,
/* eDP version 1.2 */
EDP_REVISION_12 = 0x01,
/* eDP version 1.3 */
EDP_REVISION_13 = 0x02
};
enum {
LINK_RATE_REF_FREQ_IN_KHZ = 27000 /*27MHz*/
};
struct link_training_settings {
struct dc_link_settings link_settings;
struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
bool allow_invalid_msa_timing_param;
};
enum hw_dp_training_pattern {
HW_DP_TRAINING_PATTERN_1 = 0,
HW_DP_TRAINING_PATTERN_2,
HW_DP_TRAINING_PATTERN_3,
HW_DP_TRAINING_PATTERN_4
};
/*TODO: Move this enum test harness*/
/* Test patterns*/
enum dp_test_pattern {
/* Input data is pass through Scrambler
* and 8b10b Encoder straight to output*/
DP_TEST_PATTERN_VIDEO_MODE = 0,
/* phy test patterns*/
DP_TEST_PATTERN_D102,
DP_TEST_PATTERN_SYMBOL_ERROR,
DP_TEST_PATTERN_PRBS7,
DP_TEST_PATTERN_80BIT_CUSTOM,
DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE,
/* Link Training Patterns */
DP_TEST_PATTERN_TRAINING_PATTERN1,
DP_TEST_PATTERN_TRAINING_PATTERN2,
DP_TEST_PATTERN_TRAINING_PATTERN3,
DP_TEST_PATTERN_TRAINING_PATTERN4,
/* link test patterns*/
DP_TEST_PATTERN_COLOR_SQUARES,
DP_TEST_PATTERN_COLOR_SQUARES_CEA,
DP_TEST_PATTERN_VERTICAL_BARS,
DP_TEST_PATTERN_HORIZONTAL_BARS,
DP_TEST_PATTERN_COLOR_RAMP,
/* audio test patterns*/
DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED,
DP_TEST_PATTERN_AUDIO_SAWTOOTH,
DP_TEST_PATTERN_UNSUPPORTED
};
enum dp_panel_mode {
/* not required */
DP_PANEL_MODE_DEFAULT,
/* standard mode for eDP */
DP_PANEL_MODE_EDP,
/* external chips specific settings */
DP_PANEL_MODE_SPECIAL
};
/**
* @brief LinkServiceInitOptions to set certain bits
*/
struct link_service_init_options {
uint32_t APPLY_MISALIGNMENT_BUG_WORKAROUND:1;
};
/**
* @brief data required to initialize LinkService
*/
struct link_service_init_data {
/* number of displays indices which the MST Mgr would manange*/
uint32_t num_of_displays;
enum link_service_type link_type;
/*struct mst_mgr_callback_object*topology_change_callback;*/
/* native aux access */
struct ddc_service *dpcd_access_srv;
/* for calling HWSS to program HW */
struct hw_sequencer *hwss;
/* the source which to register IRQ on */
enum dc_irq_source irq_src_hpd_rx;
enum dc_irq_source irq_src_dp_sink;
/* other init options such as SW Workarounds */
struct link_service_init_options init_options;
uint32_t connector_enum_id;
struct graphics_object_id connector_id;
struct dc_context *ctx;
struct topology_mgr *tm;
};
/* DPCD_ADDR_TRAINING_LANEx_SET registers value */
union dpcd_training_lane_set {
struct {
#if defined(LITTLEENDIAN_CPU)
uint8_t VOLTAGE_SWING_SET:2;
uint8_t MAX_SWING_REACHED:1;
uint8_t PRE_EMPHASIS_SET:2;
uint8_t MAX_PRE_EMPHASIS_REACHED:1;
/* following is reserved in DP 1.1 */
uint8_t POST_CURSOR2_SET:2;
#elif defined(BIGENDIAN_CPU)
uint8_t POST_CURSOR2_SET:2;
uint8_t MAX_PRE_EMPHASIS_REACHED:1;
uint8_t PRE_EMPHASIS_SET:2;
uint8_t MAX_SWING_REACHED:1;
uint8_t VOLTAGE_SWING_SET:2;
#else
#error ARCH not defined!
#endif
} bits;
uint8_t raw;
};
/**
* @brief represent the 16 byte
* global unique identifier
*/
struct mst_guid {
uint8_t ids[16];
};
/**
* @brief represents the relative address used
* to identify a node in MST topology network
*/
struct mst_rad {
/* number of links. rad[0] up to
* rad [linkCount - 1] are valid. */
uint32_t rad_link_count;
/* relative address. rad[0] is the
* first device connected to the source. */
uint8_t rad[15];
/* extra 10 bytes for underscores; for e.g.:2_1_8*/
int8_t rad_str[25];
};
/* DP MST stream allocation (payload bandwidth number) */
struct dp_mst_stream_allocation {
uint8_t vcp_id;
/* number of slots required for the DP stream in
* transport packet */
uint8_t slot_count;
};
/* DP MST stream allocation table */
struct dp_mst_stream_allocation_table {
/* number of DP video streams */
int stream_count;
/* array of stream allocations */
struct dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
};
#endif /*__DAL_LINK_SERVICE_TYPES_H__*/

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_LOGGER_INTERFACE_H__
#define __DAL_LOGGER_INTERFACE_H__
#include "logger_types.h"
struct dc_context;
struct dc_link;
struct dc_surface_update;
/*
*
* DAL logger functionality
*
*/
struct dal_logger *dal_logger_create(struct dc_context *ctx);
uint32_t dal_logger_destroy(struct dal_logger **logger);
void dm_logger_write(
struct dal_logger *logger,
enum dc_log_type log_type,
const char *msg,
...);
void dm_logger_append(
struct log_entry *entry,
const char *msg,
...);
void dm_logger_open(
struct dal_logger *logger,
struct log_entry *entry,
enum dc_log_type log_type);
void dm_logger_close(struct log_entry *entry);
void dc_conn_log(struct dc_context *ctx,
const struct dc_link *link,
uint8_t *hex_data,
int hex_data_count,
enum dc_log_type event,
const char *msg,
...);
void logger_write(struct dal_logger *logger,
enum dc_log_type log_type,
const char *msg,
void *paralist);
void pre_surface_trace(
const struct dc *dc,
const struct dc_surface *const *surfaces,
int surface_count);
void update_surface_trace(
const struct dc *dc,
const struct dc_surface_update *updates,
int surface_count);
void post_surface_trace(const struct dc *dc);
/* Any function which is empty or have incomplete implementation should be
* marked by this macro.
* Note that the message will be printed exactly once for every function
* it is used in order to avoid repeating of the same message. */
#define DAL_LOGGER_NOT_IMPL(fmt, ...) \
{ \
static bool print_not_impl = true; \
\
if (print_not_impl == true) { \
print_not_impl = false; \
dm_logger_write(ctx->logger, LOG_WARNING, \
"DAL_NOT_IMPL: " fmt, ##__VA_ARGS__); \
} \
}
/******************************************************************************
* Convenience macros to save on typing.
*****************************************************************************/
#define DC_ERROR(...) \
dm_logger_write(dc_ctx->logger, LOG_ERROR, \
__VA_ARGS__);
#define DC_SYNC_INFO(...) \
dm_logger_write(dc_ctx->logger, LOG_SYNC, \
__VA_ARGS__);
/* Connectivity log format:
* [time stamp] [drm] [Major_minor] [connector name] message.....
* eg:
* [ 26.590965] [drm] [Conn_LKTN] [DP-1] HBRx4 pass VS=0, PE=0^
* [ 26.881060] [drm] [Conn_Mode] [DP-1] {2560x1080, 2784x1111@185580Khz}^
*/
#define CONN_DATA_DETECT(link, hex_data, hex_len, ...) \
dc_conn_log(link->ctx, &link->public, hex_data, hex_len, \
LOG_EVENT_DETECTION, ##__VA_ARGS__)
#define CONN_DATA_LINK_LOSS(link, hex_data, hex_len, ...) \
dc_conn_log(link->ctx, &link->public, hex_data, hex_len, \
LOG_EVENT_LINK_LOSS, ##__VA_ARGS__)
#define CONN_MSG_LT(link, ...) \
dc_conn_log(link->ctx, &link->public, NULL, 0, \
LOG_EVENT_LINK_TRAINING, ##__VA_ARGS__)
#define CONN_MSG_MODE(link, ...) \
dc_conn_log(link->ctx, &link->public, NULL, 0, \
LOG_EVENT_MODE_SET, ##__VA_ARGS__)
#endif /* __DAL_LOGGER_INTERFACE_H__ */

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_LOGGER_TYPES_H__
#define __DAL_LOGGER_TYPES_H__
#include "os_types.h"
#define MAX_NAME_LEN 32
struct dal_logger;
enum dc_log_type {
LOG_ERROR = 0,
LOG_WARNING,
LOG_DC,
LOG_SURFACE,
LOG_HW_HOTPLUG,
LOG_HW_LINK_TRAINING,
LOG_HW_SET_MODE,
LOG_HW_RESUME_S3,
LOG_HW_AUDIO,
LOG_HW_HPD_IRQ,
LOG_MST,
LOG_SCALER,
LOG_BIOS,
LOG_BANDWIDTH_CALCS,
LOG_BANDWIDTH_VALIDATION,
LOG_I2C_AUX,
LOG_SYNC,
LOG_BACKLIGHT,
LOG_FEATURE_OVERRIDE,
LOG_DETECTION_EDID_PARSER,
LOG_DETECTION_DP_CAPS,
LOG_RESOURCE,
LOG_DML,
LOG_EVENT_MODE_SET,
LOG_EVENT_DETECTION,
LOG_EVENT_LINK_TRAINING,
LOG_EVENT_LINK_LOSS,
LOG_EVENT_UNDERFLOW,
LOG_IF_TRACE,
LOG_SECTION_TOTAL_COUNT
};
union logger_flags {
struct {
uint32_t ENABLE_CONSOLE:1; /* Print to console */
uint32_t ENABLE_BUFFER:1; /* Print to buffer */
uint32_t RESERVED:30;
} bits;
uint32_t value;
};
struct log_entry {
struct dal_logger *logger;
enum dc_log_type type;
char *buf;
uint32_t buf_offset;
uint32_t max_buf_bytes;
};
/**
* Structure for enumerating log types
*/
struct dc_log_type_info {
enum dc_log_type type;
char name[MAX_NAME_LEN];
};
#endif /* __DAL_LOGGER_TYPES_H__ */

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_SET_MODE_TYPES_H__
#define __DAL_SET_MODE_TYPES_H__
#include "dc_types.h"
/* Info frame packet status */
enum info_frame_flag {
INFO_PACKET_PACKET_INVALID = 0,
INFO_PACKET_PACKET_VALID = 1,
INFO_PACKET_PACKET_RESET = 2,
INFO_PACKET_PACKET_UPDATE_SCAN_TYPE = 8
};
/* Info frame types */
enum info_frame_type {
INFO_FRAME_GAMUT = 0x0A,
INFO_FRAME_VENDOR_INFO = 0x81,
INFO_FRAME_AVI = 0x82
};
/* Info frame versions */
enum info_frame_version {
INFO_FRAME_VERSION_1 = 1,
INFO_FRAME_VERSION_2 = 2,
INFO_FRAME_VERSION_3 = 3
};
/* Info frame size */
enum info_frame_size {
INFO_FRAME_SIZE_AVI = 13,
INFO_FRAME_SIZE_VENDOR = 25,
INFO_FRAME_SIZE_AUDIO = 10
};
struct hdmi_info_frame_header {
uint8_t info_frame_type;
uint8_t version;
uint8_t length;
};
#pragma pack(push)
#pragma pack(1)
struct info_packet_raw_data {
uint8_t hb0;
uint8_t hb1;
uint8_t hb2;
uint8_t sb[28]; /* sb0~sb27 */
};
union hdmi_info_packet {
struct avi_info_frame {
struct hdmi_info_frame_header header;
uint8_t CHECK_SUM:8;
uint8_t S0_S1:2;
uint8_t B0_B1:2;
uint8_t A0:1;
uint8_t Y0_Y1_Y2:3;
uint8_t R0_R3:4;
uint8_t M0_M1:2;
uint8_t C0_C1:2;
uint8_t SC0_SC1:2;
uint8_t Q0_Q1:2;
uint8_t EC0_EC2:3;
uint8_t ITC:1;
uint8_t VIC0_VIC7:8;
uint8_t PR0_PR3:4;
uint8_t CN0_CN1:2;
uint8_t YQ0_YQ1:2;
uint16_t bar_top;
uint16_t bar_bottom;
uint16_t bar_left;
uint16_t bar_right;
uint8_t reserved[14];
} bits;
struct info_packet_raw_data packet_raw_data;
};
struct info_packet {
enum info_frame_flag flags;
union hdmi_info_packet info_packet_hdmi;
};
struct info_frame {
struct info_packet avi_info_packet;
struct info_packet gamut_packet;
struct info_packet vendor_info_packet;
struct info_packet spd_info_packet;
};
#pragma pack(pop)
#endif /* __DAL_SET_MODE_TYPES_H__ */

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_SIGNAL_TYPES_H__
#define __DC_SIGNAL_TYPES_H__
enum signal_type {
SIGNAL_TYPE_NONE = 0L, /* no signal */
SIGNAL_TYPE_DVI_SINGLE_LINK = (1 << 0),
SIGNAL_TYPE_DVI_DUAL_LINK = (1 << 1),
SIGNAL_TYPE_HDMI_TYPE_A = (1 << 2),
SIGNAL_TYPE_LVDS = (1 << 3),
SIGNAL_TYPE_RGB = (1 << 4),
SIGNAL_TYPE_DISPLAY_PORT = (1 << 5),
SIGNAL_TYPE_DISPLAY_PORT_MST = (1 << 6),
SIGNAL_TYPE_EDP = (1 << 7),
SIGNAL_TYPE_WIRELESS = (1 << 8), /* Wireless Display */
SIGNAL_TYPE_VIRTUAL = (1 << 9), /* Virtual Display */
SIGNAL_TYPE_COUNT = 10,
SIGNAL_TYPE_ALL = (1 << SIGNAL_TYPE_COUNT) - 1
};
/* help functions for signal types manipulation */
bool dc_is_hdmi_signal(enum signal_type signal);
bool dc_is_dp_sst_signal(enum signal_type signal);
bool dc_is_dp_signal(enum signal_type signal);
bool dc_is_dp_external_signal(enum signal_type signal);
bool dc_is_analog_signal(enum signal_type signal);
bool dc_is_embedded_signal(enum signal_type signal);
bool dc_is_dvi_signal(enum signal_type signal);
bool dc_is_dvi_single_link_signal(enum signal_type signal);
bool dc_is_dual_link_signal(enum signal_type signal);
bool dc_is_audio_capable_signal(enum signal_type signal);
bool dc_is_digital_encoder_compatible_signal(enum signal_type signal);
#endif

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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_VECTOR_H__
#define __DAL_VECTOR_H__
struct vector {
uint8_t *container;
uint32_t struct_size;
uint32_t count;
uint32_t capacity;
struct dc_context *ctx;
};
bool dal_vector_construct(
struct vector *vector,
struct dc_context *ctx,
uint32_t capacity,
uint32_t struct_size);
struct vector *dal_vector_create(
struct dc_context *ctx,
uint32_t capacity,
uint32_t struct_size);
/* 'initial_value' is optional. If initial_value not supplied,
* each "structure" in the vector will contain zeros by default. */
struct vector *dal_vector_presized_create(
struct dc_context *ctx,
uint32_t size,
void *initial_value,
uint32_t struct_size);
void dal_vector_destruct(
struct vector *vector);
void dal_vector_destroy(
struct vector **vector);
uint32_t dal_vector_get_count(
const struct vector *vector);
/* dal_vector_insert_at
* reallocate container if necessary
* then shell items at right and insert
* return if the container modified
* do not check that index belongs to container
* since the function is private and index is going to be calculated
* either with by function or as get_count+1 */
bool dal_vector_insert_at(
struct vector *vector,
const void *what,
uint32_t position);
bool dal_vector_append(
struct vector *vector,
const void *item);
/* operator[] */
void *dal_vector_at_index(
const struct vector *vector,
uint32_t index);
void dal_vector_set_at_index(
const struct vector *vector,
const void *what,
uint32_t index);
/* create a clone (copy) of a vector */
struct vector *dal_vector_clone(
const struct vector *vector_other);
/* dal_vector_remove_at_index
* Shifts elements on the right from remove position to the left,
* removing an element at position by overwrite means*/
bool dal_vector_remove_at_index(
struct vector *vector,
uint32_t index);
uint32_t dal_vector_capacity(const struct vector *vector);
bool dal_vector_reserve(struct vector *vector, uint32_t capacity);
void dal_vector_clear(struct vector *vector);
/***************************************************************************
* Macro definitions of TYPE-SAFE versions of vector set/get functions.
***************************************************************************/
#define DAL_VECTOR_INSERT_AT(vector_type, type_t) \
static bool vector_type##_vector_insert_at( \
struct vector *vector, \
type_t what, \
uint32_t position) \
{ \
return dal_vector_insert_at(vector, what, position); \
}
#define DAL_VECTOR_APPEND(vector_type, type_t) \
static bool vector_type##_vector_append( \
struct vector *vector, \
type_t item) \
{ \
return dal_vector_append(vector, item); \
}
/* Note: "type_t" is the ONLY token accepted by "checkpatch.pl" and by
* "checkcommit" as *return type*.
* For uniformity reasons "type_t" is used for all type-safe macro
* definitions here. */
#define DAL_VECTOR_AT_INDEX(vector_type, type_t) \
static type_t vector_type##_vector_at_index( \
const struct vector *vector, \
uint32_t index) \
{ \
return dal_vector_at_index(vector, index); \
}
#define DAL_VECTOR_SET_AT_INDEX(vector_type, type_t) \
static void vector_type##_vector_set_at_index( \
const struct vector *vector, \
type_t what, \
uint32_t index) \
{ \
dal_vector_set_at_index(vector, what, index); \
}
#endif /* __DAL_VECTOR_H__ */