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drm/amd/dc: Add dc display driver (v2)
Supported DCE versions: 8.0, 10.0, 11.0, 11.2 v2: rebase against 4.11 Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland
committed by
Alex Deucher
Alex Deucher
parent
9c5b2b0d40
commit
4562236b3b
175
drivers/gpu/drm/amd/display/include/display_clock_interface.h
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175
drivers/gpu/drm/amd/display/include/display_clock_interface.h
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/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DISPLAY_CLOCK_INTERFACE_H__
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#define __DISPLAY_CLOCK_INTERFACE_H__
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#include "hw_sequencer_types.h"
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#include "grph_object_defs.h"
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#include "signal_types.h"
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/* Timing related information*/
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struct dc_timing_params {
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uint32_t INTERLACED:1;
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uint32_t HCOUNT_BY_TWO:1;
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uint32_t PIXEL_REPETITION:4; /*< values 1 to 10 supported*/
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uint32_t PREFETCH:1;
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uint32_t h_total;
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uint32_t h_addressable;
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uint32_t h_sync_width;
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};
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/* Scaling related information*/
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struct dc_scaling_params {
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uint32_t h_overscan_right;
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uint32_t h_overscan_left;
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uint32_t h_taps;
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uint32_t v_taps;
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};
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/* VScalerEfficiency */
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enum v_scaler_efficiency {
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V_SCALER_EFFICIENCY_LB36BPP = 0,
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V_SCALER_EFFICIENCY_LB30BPP = 1,
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V_SCALER_EFFICIENCY_LB24BPP = 2,
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V_SCALER_EFFICIENCY_LB18BPP = 3
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};
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/* Parameters required for minimum Engine
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* and minimum Display clock calculations*/
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struct min_clock_params {
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uint32_t id;
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uint32_t requested_pixel_clock; /* in KHz */
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uint32_t actual_pixel_clock; /* in KHz */
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struct view source_view;
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struct view dest_view;
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struct dc_timing_params timing_info;
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struct dc_scaling_params scaling_info;
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enum signal_type signal_type;
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enum dc_color_depth deep_color_depth;
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enum v_scaler_efficiency scaler_efficiency;
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bool line_buffer_prefetch_enabled;
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};
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/* Result of Minimum System and Display clock calculations.
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* Minimum System clock and Display clock, source and path to be used
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* for Display clock*/
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struct minimum_clocks_calculation_result {
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uint32_t min_sclk_khz;
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uint32_t min_dclk_khz;
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uint32_t min_mclk_khz;
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uint32_t min_deep_sleep_sclk;
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};
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/* Enumeration of all clocks states */
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enum clocks_state {
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CLOCKS_STATE_INVALID = 0,
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CLOCKS_STATE_ULTRA_LOW,
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CLOCKS_STATE_LOW,
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CLOCKS_STATE_NOMINAL,
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CLOCKS_STATE_PERFORMANCE,
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/* Starting from DCE11, Max 8 level DPM state supported */
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CLOCKS_DPM_STATE_LEVEL_INVALID = CLOCKS_STATE_INVALID,
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CLOCKS_DPM_STATE_LEVEL_0 = CLOCKS_STATE_ULTRA_LOW,
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CLOCKS_DPM_STATE_LEVEL_1 = CLOCKS_STATE_LOW,
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CLOCKS_DPM_STATE_LEVEL_2 = CLOCKS_STATE_NOMINAL,
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CLOCKS_DPM_STATE_LEVEL_3 = CLOCKS_STATE_PERFORMANCE,
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CLOCKS_DPM_STATE_LEVEL_4 = CLOCKS_DPM_STATE_LEVEL_3 + 1,
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CLOCKS_DPM_STATE_LEVEL_5 = CLOCKS_DPM_STATE_LEVEL_4 + 1,
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CLOCKS_DPM_STATE_LEVEL_6 = CLOCKS_DPM_STATE_LEVEL_5 + 1,
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CLOCKS_DPM_STATE_LEVEL_7 = CLOCKS_DPM_STATE_LEVEL_6 + 1,
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};
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/* Structure containing all state-dependent clocks
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* (dependent on "enum clocks_state") */
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struct state_dependent_clocks {
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uint32_t display_clk_khz;
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uint32_t pixel_clk_khz;
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};
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struct display_clock_state {
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uint32_t DFS_BYPASS_ACTIVE:1;
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};
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struct display_clock;
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struct display_clock *dal_display_clock_dce112_create(
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struct dc_context *ctx);
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struct display_clock *dal_display_clock_dce110_create(
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struct dc_context *ctx);
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struct display_clock *dal_display_clock_dce80_create(
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struct dc_context *ctx);
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void dal_display_clock_destroy(struct display_clock **to_destroy);
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bool dal_display_clock_validate(
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struct display_clock *disp_clk,
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struct min_clock_params *params);
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uint32_t dal_display_clock_calculate_min_clock(
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struct display_clock *disp_clk,
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uint32_t path_num,
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struct min_clock_params *params);
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uint32_t dal_display_clock_get_validation_clock(struct display_clock *disp_clk);
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void dal_display_clock_set_clock(
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struct display_clock *disp_clk,
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uint32_t requested_clock_khz);
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uint32_t dal_display_clock_get_clock(struct display_clock *disp_clk);
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bool dal_display_clock_get_min_clocks_state(
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struct display_clock *disp_clk,
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enum clocks_state *clocks_state);
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bool dal_display_clock_get_required_clocks_state(
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struct display_clock *disp_clk,
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struct state_dependent_clocks *req_clocks,
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enum clocks_state *clocks_state);
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bool dal_display_clock_set_min_clocks_state(
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struct display_clock *disp_clk,
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enum clocks_state clocks_state);
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uint32_t dal_display_clock_get_dp_ref_clk_frequency(
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struct display_clock *disp_clk);
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/*the second parameter of "switchreferenceclock" is
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* a dummy argument for all pre dce 6.0 versions*/
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void dal_display_clock_switch_reference_clock(
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struct display_clock *disp_clk,
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bool use_external_ref_clk,
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uint32_t requested_clock_khz);
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void dal_display_clock_set_dp_ref_clock_source(
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struct display_clock *disp_clk,
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enum clock_source_id clk_src);
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void dal_display_clock_store_max_clocks_state(
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struct display_clock *disp_clk,
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enum clocks_state max_clocks_state);
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void dal_display_clock_set_clock_state(
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struct display_clock *disp_clk,
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struct display_clock_state clk_state);
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struct display_clock_state dal_display_clock_get_clock_state(
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struct display_clock *disp_clk);
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uint32_t dal_display_clock_get_dfs_bypass_threshold(
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struct display_clock *disp_clk);
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void dal_display_clock_invalid_clock_state(
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struct display_clock *disp_clk);
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#endif /* __DISPLAY_CLOCK_INTERFACE_H__ */
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