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dt-bindings: clock: Convert img,pistachio-clk to DT schema

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Signed-off-by: Rob Herring (Arm) <robh@kernel.org>

Link: https://lore.kernel.org/r/20250521210712.59742-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Rob Herring (Arm)
2025-05-21 16:07:11 -05:00
committed by Stephen Boyd
parent 100026f4b5
commit 46dba2e6a3
2 changed files with 136 additions and 123 deletions
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136
Documentation/devicetree/bindings/clock/img,pistachio-clk.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/img,pistachio-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Imagination Technologies Pistachio SoC clock controllers
maintainers:
- Andrew Bresticker <abrestic@chromium.org>
description: |
Pistachio has four clock controllers (core clock, peripheral clock, peripheral
general control, and top general control) which are instantiated individually
from the device-tree.
Core clock controller:
The core clock controller generates clocks for the CPU, RPU (WiFi + BT
co-processor), audio, and several peripherals.
Peripheral clock controller:
The peripheral clock controller generates clocks for the DDR, ROM, and other
peripherals. The peripheral system clock ("periph_sys") generated by the core
clock controller is the input clock to the peripheral clock controller.
Peripheral general control:
The peripheral general control block generates system interface clocks and
resets for various peripherals. It also contains miscellaneous peripheral
control registers.
Top-level general control:
The top-level general control block contains miscellaneous control registers
and gates for the external clocks "audio_clk_in" and "enet_clk_in".
properties:
compatible:
items:
- enum:
- img,pistachio-clk
- img,pistachio-clk-periph
- img,pistachio-cr-periph
- img,pistachio-cr-top
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
minItems: 1
maxItems: 3
clock-names:
minItems: 1
maxItems: 3
required:
- compatible
- reg
- '#clock-cells'
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
const: img,pistachio-clk
then:
properties:
clocks:
items:
- description: External 52Mhz oscillator
- description: Alternate audio reference clock
- description: Alternate ethernet PHY clock
clock-names:
items:
- const: xtal
- const: audio_refclk_ext_gate
- const: ext_enet_in_gate
- if:
properties:
compatible:
contains:
const: img,pistachio-clk-periph
then:
properties:
clocks:
items:
- description: Peripheral system clock
clock-names:
items:
- const: periph_sys_core
- if:
properties:
compatible:
contains:
const: img,pistachio-cr-periph
then:
properties:
clocks:
items:
- description: System interface clock
clock-names:
items:
- const: sys
- if:
properties:
compatible:
contains:
const: img,pistachio-cr-top
then:
properties:
clocks:
items:
- description: External audio reference clock
- description: External ethernet PHY clock
clock-names:
items:
- const: audio_clk_in
- const: enet_clk_in
additionalProperties: false

123
Documentation/devicetree/bindings/clock/pistachio-clock.txt
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Imagination Technologies Pistachio SoC clock controllers
========================================================
Pistachio has four clock controllers (core clock, peripheral clock, peripheral
general control, and top general control) which are instantiated individually
from the device-tree.
External clocks:
----------------
There are three external inputs to the clock controllers which should be
defined with the following clock-output-names:
- "xtal": External 52Mhz oscillator (required)
- "audio_clk_in": Alternate audio reference clock (optional)
- "enet_clk_in": Alternate ethernet PHY clock (optional)
Core clock controller:
----------------------
The core clock controller generates clocks for the CPU, RPU (WiFi + BT
co-processor), audio, and several peripherals.
Required properties:
- compatible: Must be "img,pistachio-clk".
- reg: Must contain the base address and length of the core clock controller.
- #clock-cells: Must be 1. The single cell is the clock identifier.
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
- clocks: Must contain an entry for each clock in clock-names.
- clock-names: Must include "xtal" (see "External clocks") and
"audio_clk_in_gate", "enet_clk_in_gate" which are generated by the
top-level general control.
Example:
clk_core: clock-controller@18144000 {
compatible = "img,pistachio-clk";
reg = <0x18144000 0x800>;
clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
<&cr_top EXT_CLK_ENET_IN>;
clock-names = "xtal", "audio_clk_in_gate", "enet_clk_in_gate";
#clock-cells = <1>;
};
Peripheral clock controller:
----------------------------
The peripheral clock controller generates clocks for the DDR, ROM, and other
peripherals. The peripheral system clock ("periph_sys") generated by the core
clock controller is the input clock to the peripheral clock controller.
Required properties:
- compatible: Must be "img,pistachio-periph-clk".
- reg: Must contain the base address and length of the peripheral clock
controller.
- #clock-cells: Must be 1. The single cell is the clock identifier.
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
- clocks: Must contain an entry for each clock in clock-names.
- clock-names: Must include "periph_sys", the peripheral system clock generated
by the core clock controller.
Example:
clk_periph: clock-controller@18144800 {
compatible = "img,pistachio-clk-periph";
reg = <0x18144800 0x800>;
clocks = <&clk_core CLK_PERIPH_SYS>;
clock-names = "periph_sys";
#clock-cells = <1>;
};
Peripheral general control:
---------------------------
The peripheral general control block generates system interface clocks and
resets for various peripherals. It also contains miscellaneous peripheral
control registers. The system clock ("sys") generated by the peripheral clock
controller is the input clock to the system clock controller.
Required properties:
- compatible: Must include "img,pistachio-periph-cr" and "syscon".
- reg: Must contain the base address and length of the peripheral general
control registers.
- #clock-cells: Must be 1. The single cell is the clock identifier.
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
- clocks: Must contain an entry for each clock in clock-names.
- clock-names: Must include "sys", the system clock generated by the peripheral
clock controller.
Example:
cr_periph: syscon@18144800 {
compatible = "img,pistachio-cr-periph", "syscon";
reg = <0x18148000 0x1000>;
clocks = <&clock_periph PERIPH_CLK_PERIPH_SYS>;
clock-names = "sys";
#clock-cells = <1>;
};
Top-level general control:
--------------------------
The top-level general control block contains miscellaneous control registers and
gates for the external clocks "audio_clk_in" and "enet_clk_in".
Required properties:
- compatible: Must include "img,pistachio-cr-top" and "syscon".
- reg: Must contain the base address and length of the top-level
control registers.
- clocks: Must contain an entry for each clock in clock-names.
- clock-names: Two optional clocks, "audio_clk_in" and "enet_clk_in" (see
"External clocks").
- #clock-cells: Must be 1. The single cell is the clock identifier.
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
Example:
cr_top: syscon@18144800 {
compatible = "img,pistachio-cr-top", "syscon";
reg = <0x18149000 0x200>;
clocks = <&audio_refclk>, <&ext_enet_in>;
clock-names = "audio_clk_in", "enet_clk_in";
#clock-cells = <1>;
};