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drm/panthor: add custom ASN_HASH support for mt8196

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Add panthor_soc_data to control custom ASN_HASH. Add compatible string
for "mediatek,mt8196-mali" and enable custom ASN_HASH for the soc.

Without custom ASN_HASH, FW fails to boot

  panthor 48000000.gpu: [drm] *ERROR* Unhandled Page fault in AS0 at VA 0x0000000000000000
  panthor 48000000.gpu: [drm] *ERROR* Failed to boot MCU (status=fatal)
  panthor 48000000.gpu: probe with driver panthor failed with error -110

With custom ASN_HASH, panthor probes fine and userspace boots to ui just
fine as well

  panthor 48000000.gpu: [drm] clock rate = 0
  panthor 48000000.gpu: EM: created perf domain
  panthor 48000000.gpu: [drm] Mali-G925-Immortalis id 0xd830 major 0x0 minor 0x1 status 0x5
  panthor 48000000.gpu: [drm] Features: L2:0x8130306 Tiler:0x809 Mem:0x301 MMU:0x2830 AS:0xff
  panthor 48000000.gpu: [drm] shader_present=0xee0077 l2_present=0x1 tiler_present=0x1
  panthor 48000000.gpu: [drm] Firmware protected mode entry not be supported, ignoring
  panthor 48000000.gpu: [drm] Firmware git sha: 27713280172c742d467a4b7d11180930094092ec
  panthor 48000000.gpu: [drm] CSF FW using interface v3.13.0, Features 0x10 Instrumentation features 0x71
  [drm] Initialized panthor 1.5.0 for 48000000.gpu on minor 1

Note that the clock and the regulator drivers are not upstreamed yet.
They might as well take a different form when upstreamed.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
Link: https://lore.kernel.org/r/20250913002155.1163908-3-olvaffe@gmail.com
This commit is contained in:
Chia-I Wu
2025-09-12 17:21:55 -07:00
committed by Steven Price
parent 4b478288ca
commit 4e04683022
5 changed files with 50 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/gpu/drm/panthor/panthor_device.h
View File

@@ -31,6 +31,17 @@ struct panthor_perfcnt;
struct panthor_vm;
struct panthor_vm_pool;
/**
* struct panthor_soc_data - Panthor SoC Data
*/
struct panthor_soc_data {
/** @asn_hash_enable: True if GPU_L2_CONFIG_ASN_HASH_ENABLE must be set. */
bool asn_hash_enable;
/** @asn_hash: ASN_HASH values when asn_hash_enable is true. */
u32 asn_hash[3];
};
/**
* enum panthor_device_pm_state - PM state
*/
@@ -93,6 +104,9 @@ struct panthor_device {
/** @base: Base drm_device. */
struct drm_device base;
/** @soc_data: Optional SoC data. */
const struct panthor_soc_data *soc_data;
/** @phys_addr: Physical address of the iomem region. */
phys_addr_t phys_addr;