drm/amd/display: Set DFS bypass flags for dce110

[Why]

While there is support for using and quering DFS bypass clocks the
hardware is never notified to enter DFS bypass mode for dce110.

[How]

Add a flag that can be set when programming the display engine PLL
to enable DFS bypass mode. If this flag is set then the hardware is
notified to enter DFS bypass mode and the correct display engine clock
frequency can be acquired.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Kazlauskas
2018-07-24 13:19:49 -04:00
committed by Alex Deucher
parent 2cb3bcdb33
commit 4e60536d09
3 changed files with 8 additions and 0 deletions

View File

@@ -2201,6 +2201,9 @@ static enum bp_result program_clock_v6(
if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
params.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
if (bp_params->flags.SET_DISPCLK_DFS_BYPASS)
params.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS;
if (EXEC_BIOS_CMD_TABLE(SetPixelClock, params)) {
/* True display clock is returned by VBIOS if DFS bypass
* is enabled. */