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openrisc: add cacheflush support to fix icache aliasing

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On OpenRISC the icache does not snoop data stores.  This can cause
aliasing as reported by Jan. This patch fixes the issue to ensure icache
is properly synchronized when code is written to memory.  It supports both
SMP and UP flushing.

This supports dcache flush as well for architectures that do not support
write-through caches; most OpenRISC implementations do implement
write-through cache however. Dcache flushes are done only on a single
core as OpenRISC dcaches all support snooping of bus stores.

Signed-off-by: Jan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de>
[shorne@gmail.com: Squashed patches and wrote commit message]
Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Jan Henrik Weinstock
2015-11-04 17:26:10 +01:00
committed by Stafford Horne
parent c056718464
commit 4ee93d80ad
7 changed files with 194 additions and 8 deletions
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16
arch/openrisc/include/asm/pgtable.h
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@@ -416,15 +416,19 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
struct vm_area_struct;
/*
* or32 doesn't have any external MMU info: the kernel page
* tables contain all the necessary information.
*
* Actually I am not sure on what this could be used for.
*/
static inline void update_tlb(struct vm_area_struct *vma,
unsigned long address, pte_t *pte)
{
}
extern void update_cache(struct vm_area_struct *vma,
unsigned long address, pte_t *pte);
static inline void update_mmu_cache(struct vm_area_struct *vma,
unsigned long address, pte_t *pte)
{
update_tlb(vma, address, pte);
update_cache(vma, address, pte);
}
/* __PHX__ FIXME, SWAP, this probably doesn't work */