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drm/amd/display: enabling seamless boot sequence for dcn2

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[Why]
Seamless boot (building SW state inheriting BIOS-initialized timing) was
enabled on DCN2, including fixes

[How]
Includes fixes for MPC, DPPCLK, and DIG FE mapping/OTG source select/
Pixel clock.

This is part 2 of 2 for seamless boot NV10

Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Martin Leung
2019-07-17 16:08:19 -04:00
committed by Alex Deucher
parent 39bdac36cc
commit 5ec43eda85
17 changed files with 172 additions and 36 deletions
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3
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
View File

@@ -199,6 +199,9 @@ struct mpc_funcs {
* Return: void
*/
void (*mpc_init)(struct mpc *mpc);
void (*mpc_init_single_inst)(
struct mpc *mpc,
unsigned int mpcc_id);
/*
* Update the blending configuration for a specified MPCC.

3
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
View File

@@ -214,6 +214,9 @@ struct stream_encoder_funcs {
void (*hdmi_reset_stream_attribute)(
struct stream_encoder *enc);
unsigned int (*dig_source_otg)(
struct stream_encoder *enc);
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
void (*dp_set_dsc_config)(