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drm/amdgpu: add helper to read UMA carveout info

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Currently, the available UMA allocation configs in the integrated system
information table have not been parsed. Add a helper function to retrieve
and store these configs.

Co-developed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yo-Jung Leo Lin (AMD)
2025-12-12 15:59:14 +08:00
committed by Alex Deucher
parent 6f3b631e39
commit 685b7113e0
3 changed files with 113 additions and 0 deletions
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77
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
View File

@@ -296,6 +296,83 @@ static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
return vram_type;
}
static int amdgpu_atomfirmware_get_uma_carveout_info_v2_3(struct amdgpu_device *adev,
union igp_info *igp_info,
struct amdgpu_uma_carveout_info *uma_info)
{
struct uma_carveout_option *opts;
uint8_t nr_uma_options;
int i;
nr_uma_options = igp_info->v23.UMACarveoutIndexMax;
if (!nr_uma_options)
return -ENODEV;
if (nr_uma_options > MAX_UMA_OPTION_ENTRIES) {
drm_dbg(adev_to_drm(adev),
"Number of UMA options exceeds max table size. Options will not be parsed");
return -EINVAL;
}
uma_info->num_entries = nr_uma_options;
uma_info->uma_option_index = igp_info->v23.UMACarveoutIndex;
opts = igp_info->v23.UMASizeControlOption;
for (i = 0; i < nr_uma_options; i++) {
if (!opts[i].memoryCarvedGb)
uma_info->entries[i].memory_carved_mb = 512;
else
uma_info->entries[i].memory_carved_mb = (uint32_t)opts[i].memoryCarvedGb << 10;
uma_info->entries[i].flags = opts[i].uma_carveout_option_flags.all8;
strscpy(uma_info->entries[i].name, opts[i].optionName, MAX_UMA_OPTION_NAME);
}
return 0;
}
int amdgpu_atomfirmware_get_uma_carveout_info(struct amdgpu_device *adev,
struct amdgpu_uma_carveout_info *uma_info)
{
struct amdgpu_mode_info *mode_info = &adev->mode_info;
union igp_info *igp_info;
u16 data_offset, size;
u8 frev, crev;
int index;
if (!(adev->flags & AMD_IS_APU))
return -ENODEV;
index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
integratedsysteminfo);
if (!amdgpu_atom_parse_data_header(mode_info->atom_context,
index, &size,
&frev, &crev, &data_offset)) {
return -EINVAL;
}
igp_info = (union igp_info *)
(mode_info->atom_context->bios + data_offset);
switch (frev) {
case 2:
switch (crev) {
case 3:
return amdgpu_atomfirmware_get_uma_carveout_info_v2_3(adev, igp_info, uma_info);
break;
default:
break;
}
break;
default:
break;
}
return -ENODEV;
}
int
amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
int *vram_width, int *vram_type,