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Merge drm/drm-next into drm-intel-next
Backmerge to get the topic/drm-intel-plane-color-pipeline branch contents. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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@@ -7298,6 +7298,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
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struct intel_display *display = to_intel_display(state);
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struct intel_crtc_state *new_crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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unsigned int size = new_crtc_state->plane_color_changed ? 8192 : 1024;
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if (!new_crtc_state->use_flipq &&
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!new_crtc_state->use_dsb &&
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@@ -7308,10 +7309,12 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
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* Rough estimate:
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* ~64 registers per each plane * 8 planes = 512
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* Double that for pipe stuff and other overhead.
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* ~4913 registers for 3DLUT
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* ~200 color registers * 3 HDR planes
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*/
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new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0,
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new_crtc_state->use_dsb ||
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new_crtc_state->use_flipq ? 1024 : 16);
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new_crtc_state->use_flipq ? size : 16);
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if (!new_crtc_state->dsb_commit) {
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new_crtc_state->use_flipq = false;
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new_crtc_state->use_dsb = false;
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