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Merge tag 'powerpc-5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc updates from Michael Ellerman: - Support for userspace to send requests directly to the on-chip GZIP accelerator on Power9. - Rework of our lockless page table walking (__find_linux_pte()) to make it safe against parallel page table manipulations without relying on an IPI for serialisation. - A series of fixes & enhancements to make our machine check handling more robust. - Lots of plumbing to add support for "prefixed" (64-bit) instructions on Power10. - Support for using huge pages for the linear mapping on 8xx (32-bit). - Remove obsolete Xilinx PPC405/PPC440 support, and an associated sound driver. - Removal of some obsolete 40x platforms and associated cruft. - Initial support for booting on Power10. - Lots of other small features, cleanups & fixes. Thanks to: Alexey Kardashevskiy, Alistair Popple, Andrew Donnellan, Andrey Abramov, Aneesh Kumar K.V, Balamuruhan S, Bharata B Rao, Bulent Abali, Cédric Le Goater, Chen Zhou, Christian Zigotzky, Christophe JAILLET, Christophe Leroy, Dmitry Torokhov, Emmanuel Nicolet, Erhard F., Gautham R. Shenoy, Geoff Levand, George Spelvin, Greg Kurz, Gustavo A. R. Silva, Gustavo Walbon, Haren Myneni, Hari Bathini, Joel Stanley, Jordan Niethe, Kajol Jain, Kees Cook, Leonardo Bras, Madhavan Srinivasan., Mahesh Salgaonkar, Markus Elfring, Michael Neuling, Michal Simek, Nathan Chancellor, Nathan Lynch, Naveen N. Rao, Nicholas Piggin, Oliver O'Halloran, Paul Mackerras, Pingfan Liu, Qian Cai, Ram Pai, Raphael Moreira Zinsly, Ravi Bangoria, Sam Bobroff, Sandipan Das, Segher Boessenkool, Stephen Rothwell, Sukadev Bhattiprolu, Tyrel Datwyler, Wolfram Sang, Xiongfeng Wang. * tag 'powerpc-5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (299 commits) powerpc/pseries: Make vio and ibmebus initcalls pseries specific cxl: Remove dead Kconfig options powerpc: Add POWER10 architected mode powerpc/dt_cpu_ftrs: Add MMA feature powerpc/dt_cpu_ftrs: Enable Prefixed Instructions powerpc/dt_cpu_ftrs: Advertise support for ISA v3.1 if selected powerpc: Add support for ISA v3.1 powerpc: Add new HWCAP bits powerpc/64s: Don't set FSCR bits in INIT_THREAD powerpc/64s: Save FSCR to init_task.thread.fscr after feature init powerpc/64s: Don't let DT CPU features set FSCR_DSCR powerpc/64s: Don't init FSCR_DSCR in __init_FSCR() powerpc/32s: Fix another build failure with CONFIG_PPC_KUAP_DEBUG powerpc/module_64: Use special stub for _mcount() with -mprofile-kernel powerpc/module_64: Simplify check for -mprofile-kernel ftrace relocations powerpc/module_64: Consolidate ftrace code powerpc/32: Disable KASAN with pages bigger than 16k powerpc/uaccess: Don't set KUEP by default on book3s/32 powerpc/uaccess: Don't set KUAP by default on book3s/32 powerpc/8xx: Reduce time spent in allow_user_access() and friends ...
This commit is contained in:
Linus Torvalds
@@ -187,14 +187,14 @@ int map_kernel_page(unsigned long va, phys_addr_t pa, pgprot_t prot);
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* memory shall not share segments.
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*/
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#if defined(CONFIG_STRICT_KERNEL_RWX) && defined(CONFIG_MODULES)
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#define VMALLOC_START ((_ALIGN((long)high_memory, 256L << 20) + VMALLOC_OFFSET) & \
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#define VMALLOC_START ((ALIGN((long)high_memory, 256L << 20) + VMALLOC_OFFSET) & \
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~(VMALLOC_OFFSET - 1))
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#else
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#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
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#endif
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#ifdef CONFIG_KASAN_VMALLOC
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#define VMALLOC_END _ALIGN_DOWN(ioremap_bot, PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT)
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#define VMALLOC_END ALIGN_DOWN(ioremap_bot, PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT)
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#else
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#define VMALLOC_END ioremap_bot
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#endif
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@@ -217,7 +217,7 @@ int map_kernel_page(unsigned long va, phys_addr_t pa, pgprot_t prot);
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*/
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#define pte_clear(mm, addr, ptep) \
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do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
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do { pte_update(mm, addr, ptep, ~_PAGE_HASHPTE, 0, 0); } while (0)
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#define pmd_none(pmd) (!pmd_val(pmd))
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#define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
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@@ -252,84 +252,68 @@ extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
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* and the PTE may be either 32 or 64 bit wide. In the later case,
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* when using atomic updates, only the low part of the PTE is
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* accessed atomically.
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*
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* In addition, on 44x, we also maintain a global flag indicating
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* that an executable user mapping was modified, which is needed
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* to properly flush the virtually tagged instruction cache of
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* those implementations.
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*/
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#ifndef CONFIG_PTE_64BIT
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static inline unsigned long pte_update(pte_t *p,
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unsigned long clr,
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unsigned long set)
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static inline pte_basic_t pte_update(struct mm_struct *mm, unsigned long addr, pte_t *p,
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unsigned long clr, unsigned long set, int huge)
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{
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unsigned long old, tmp;
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__asm__ __volatile__("\
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1: lwarx %0,0,%3\n\
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andc %1,%0,%4\n\
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or %1,%1,%5\n"
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" stwcx. %1,0,%3\n\
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bne- 1b"
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: "=&r" (old), "=&r" (tmp), "=m" (*p)
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: "r" (p), "r" (clr), "r" (set), "m" (*p)
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: "cc" );
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return old;
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}
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#else /* CONFIG_PTE_64BIT */
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static inline unsigned long long pte_update(pte_t *p,
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unsigned long clr,
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unsigned long set)
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{
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unsigned long long old;
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pte_basic_t old;
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unsigned long tmp;
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__asm__ __volatile__("\
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1: lwarx %L0,0,%4\n\
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lwzx %0,0,%3\n\
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andc %1,%L0,%5\n\
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or %1,%1,%6\n"
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" stwcx. %1,0,%4\n\
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bne- 1b"
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__asm__ __volatile__(
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#ifndef CONFIG_PTE_64BIT
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"1: lwarx %0, 0, %3\n"
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" andc %1, %0, %4\n"
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#else
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"1: lwarx %L0, 0, %3\n"
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" lwz %0, -4(%3)\n"
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" andc %1, %L0, %4\n"
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#endif
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" or %1, %1, %5\n"
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" stwcx. %1, 0, %3\n"
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" bne- 1b"
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: "=&r" (old), "=&r" (tmp), "=m" (*p)
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: "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
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#ifndef CONFIG_PTE_64BIT
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: "r" (p),
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#else
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: "b" ((unsigned long)(p) + 4),
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#endif
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"r" (clr), "r" (set), "m" (*p)
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: "cc" );
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return old;
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}
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#endif /* CONFIG_PTE_64BIT */
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/*
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* 2.6 calls this without flushing the TLB entry; this is wrong
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* for our hash-based implementation, we fix that up here.
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*/
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#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
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static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
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static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
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unsigned long addr, pte_t *ptep)
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{
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unsigned long old;
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old = pte_update(ptep, _PAGE_ACCESSED, 0);
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old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
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if (old & _PAGE_HASHPTE) {
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unsigned long ptephys = __pa(ptep) & PAGE_MASK;
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flush_hash_pages(context, addr, ptephys, 1);
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flush_hash_pages(mm->context.id, addr, ptephys, 1);
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}
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return (old & _PAGE_ACCESSED) != 0;
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}
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#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
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__ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
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__ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep)
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#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
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static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep)
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{
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return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
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return __pte(pte_update(mm, addr, ptep, ~_PAGE_HASHPTE, 0, 0));
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}
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#define __HAVE_ARCH_PTEP_SET_WRPROTECT
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static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep)
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{
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pte_update(ptep, _PAGE_RW, 0);
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pte_update(mm, addr, ptep, _PAGE_RW, 0, 0);
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}
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static inline void __ptep_set_access_flags(struct vm_area_struct *vma,
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@@ -340,7 +324,7 @@ static inline void __ptep_set_access_flags(struct vm_area_struct *vma,
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unsigned long set = pte_val(entry) &
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(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
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pte_update(ptep, 0, set);
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pte_update(vma->vm_mm, address, ptep, 0, set, 0);
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flush_tlb_page(vma, address);
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}
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@@ -538,7 +522,7 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
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*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
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| (pte_val(pte) & ~_PAGE_HASHPTE));
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else
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pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte));
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pte_update(mm, addr, ptep, ~_PAGE_HASHPTE, pte_val(pte), 0);
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#elif defined(CONFIG_PTE_64BIT)
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/* Second case is 32-bit with 64-bit PTE. In this case, we
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