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drm/amd/display: Add DCN2 HW Sequencer and Resource
Add DCN2 resource definition and HW Sequencer changes. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland
committed by
Alex Deucher
Alex Deucher
parent
18eaea4bf8
commit
7ed4e6352c
@@ -726,6 +726,56 @@ static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu)
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#endif //(CONFIG_DRM_AMD_DC_DCN1_0)
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#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
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static bool dcn20_lock_phy(struct dmcu *dmcu)
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{
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struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
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/* If microcontroller is not running, do nothing */
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if (dmcu->dmcu_state != DMCU_RUNNING)
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return false;
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/* waitDMCUReadyForCmd */
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REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
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/* setDMCUParam_Cmd */
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REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_LOCK);
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/* notifyDMCUMsg */
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REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
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/* waitDMCUReadyForCmd */
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REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
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return true;
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}
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static bool dcn20_unlock_phy(struct dmcu *dmcu)
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{
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struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
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/* If microcontroller is not running, do nothing */
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if (dmcu->dmcu_state != DMCU_RUNNING)
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return false;
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/* waitDMCUReadyForCmd */
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REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
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/* setDMCUParam_Cmd */
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REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_UNLOCK);
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/* notifyDMCUMsg */
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REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
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/* waitDMCUReadyForCmd */
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REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
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return true;
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}
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#endif //(CONFIG_DRM_AMD_DC_DCN2_0)
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static const struct dmcu_funcs dce_funcs = {
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.dmcu_init = dce_dmcu_init,
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.load_iram = dce_dmcu_load_iram,
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@@ -750,6 +800,21 @@ static const struct dmcu_funcs dcn10_funcs = {
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};
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#endif
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#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
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static const struct dmcu_funcs dcn20_funcs = {
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.dmcu_init = dcn10_dmcu_init,
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.load_iram = dcn10_dmcu_load_iram,
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.set_psr_enable = dcn10_dmcu_set_psr_enable,
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.setup_psr = dcn10_dmcu_setup_psr,
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.get_psr_state = dcn10_get_dmcu_psr_state,
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.set_psr_wait_loop = dcn10_psr_wait_loop,
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.get_psr_wait_loop = dcn10_get_psr_wait_loop,
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.is_dmcu_initialized = dcn10_is_dmcu_initialized,
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.lock_phy = dcn20_lock_phy,
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.unlock_phy = dcn20_unlock_phy
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};
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#endif
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static void dce_dmcu_construct(
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struct dce_dmcu *dmcu_dce,
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struct dc_context *ctx,
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@@ -812,6 +877,29 @@ struct dmcu *dcn10_dmcu_create(
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}
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#endif
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#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
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struct dmcu *dcn20_dmcu_create(
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struct dc_context *ctx,
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const struct dce_dmcu_registers *regs,
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const struct dce_dmcu_shift *dmcu_shift,
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const struct dce_dmcu_mask *dmcu_mask)
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{
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struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
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if (dmcu_dce == NULL) {
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BREAK_TO_DEBUGGER();
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return NULL;
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}
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dce_dmcu_construct(
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dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
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dmcu_dce->base.funcs = &dcn20_funcs;
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return &dmcu_dce->base;
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}
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#endif
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void dce_dmcu_destroy(struct dmcu **dmcu)
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{
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struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);
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@@ -261,6 +261,14 @@ struct dmcu *dcn10_dmcu_create(
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const struct dce_dmcu_shift *dmcu_shift,
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const struct dce_dmcu_mask *dmcu_mask);
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#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
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struct dmcu *dcn20_dmcu_create(
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struct dc_context *ctx,
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const struct dce_dmcu_registers *regs,
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const struct dce_dmcu_shift *dmcu_shift,
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const struct dce_dmcu_mask *dmcu_mask);
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#endif
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void dce_dmcu_destroy(struct dmcu **dmcu);
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static const uint32_t abm_gain_stepsize = 0x0060;
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@@ -199,6 +199,70 @@
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SR(DC_IP_REQUEST_CNTL), \
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BL_REG_LIST()
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#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
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#define HWSEQ_DCN2_REG_LIST()\
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HWSEQ_DCN_REG_LIST(), \
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HWSEQ_PIXEL_RATE_REG_LIST(OTG), \
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HWSEQ_PHYPLL_REG_LIST(OTG), \
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SR(MICROSECOND_TIME_BASE_DIV), \
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SR(MILLISECOND_TIME_BASE_DIV), \
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SR(DISPCLK_FREQ_CHANGE_CNTL), \
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SR(RBBMIF_TIMEOUT_DIS), \
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SR(RBBMIF_TIMEOUT_DIS_2), \
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SR(DCHUBBUB_CRC_CTRL), \
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SR(DPP_TOP0_DPP_CRC_CTRL), \
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SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
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SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
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SR(MPC_CRC_CTRL), \
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SR(MPC_CRC_RESULT_GB), \
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SR(MPC_CRC_RESULT_C), \
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SR(MPC_CRC_RESULT_AR), \
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SR(DOMAIN0_PG_CONFIG), \
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SR(DOMAIN1_PG_CONFIG), \
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SR(DOMAIN2_PG_CONFIG), \
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SR(DOMAIN3_PG_CONFIG), \
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SR(DOMAIN4_PG_CONFIG), \
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SR(DOMAIN5_PG_CONFIG), \
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SR(DOMAIN6_PG_CONFIG), \
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SR(DOMAIN7_PG_CONFIG), \
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SR(DOMAIN8_PG_CONFIG), \
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SR(DOMAIN9_PG_CONFIG), \
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SR(DOMAIN10_PG_CONFIG), \
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SR(DOMAIN11_PG_CONFIG), \
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SR(DOMAIN16_PG_CONFIG), \
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SR(DOMAIN17_PG_CONFIG), \
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SR(DOMAIN18_PG_CONFIG), \
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SR(DOMAIN19_PG_CONFIG), \
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SR(DOMAIN20_PG_CONFIG), \
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SR(DOMAIN21_PG_CONFIG), \
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SR(DOMAIN0_PG_STATUS), \
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SR(DOMAIN1_PG_STATUS), \
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SR(DOMAIN2_PG_STATUS), \
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SR(DOMAIN3_PG_STATUS), \
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SR(DOMAIN4_PG_STATUS), \
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SR(DOMAIN5_PG_STATUS), \
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SR(DOMAIN6_PG_STATUS), \
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SR(DOMAIN7_PG_STATUS), \
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SR(DOMAIN8_PG_STATUS), \
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SR(DOMAIN9_PG_STATUS), \
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SR(DOMAIN10_PG_STATUS), \
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SR(DOMAIN11_PG_STATUS), \
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SR(DOMAIN16_PG_STATUS), \
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SR(DOMAIN17_PG_STATUS), \
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SR(DOMAIN18_PG_STATUS), \
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SR(DOMAIN19_PG_STATUS), \
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SR(DOMAIN20_PG_STATUS), \
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SR(DOMAIN21_PG_STATUS), \
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SR(D1VGA_CONTROL), \
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SR(D2VGA_CONTROL), \
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SR(D3VGA_CONTROL), \
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SR(D4VGA_CONTROL), \
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SR(D5VGA_CONTROL), \
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SR(D6VGA_CONTROL), \
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SR(DC_IP_REQUEST_CNTL), \
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BL_REG_LIST()
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#endif
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struct dce_hwseq_registers {
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/* Backlight registers */
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@@ -453,6 +517,69 @@ struct dce_hwseq_registers {
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HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh), \
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HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
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#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
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#define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\
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HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
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HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
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HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
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HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
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HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
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HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
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HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
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HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
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HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
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HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
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HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
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HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
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HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
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HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
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HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
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HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
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HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
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HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
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HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \
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HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \
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HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \
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HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \
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HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, mask_sh), \
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HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_GATE, mask_sh), \
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HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, mask_sh), \
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HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_GATE, mask_sh), \
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HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \
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HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \
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HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \
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HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \
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HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \
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HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \
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HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \
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HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \
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HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \
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HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \
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HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, mask_sh), \
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HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_GATE, mask_sh), \
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HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
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HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
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HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
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HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
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HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
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HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
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HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
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HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
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HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \
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HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \
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HWS_SF(, DOMAIN10_PG_STATUS, DOMAIN10_PGFSM_PWR_STATUS, mask_sh), \
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HWS_SF(, DOMAIN11_PG_STATUS, DOMAIN11_PGFSM_PWR_STATUS, mask_sh), \
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HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \
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HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
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HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
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HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \
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HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \
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HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \
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HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
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HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
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HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
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#endif
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#define HWSEQ_REG_FIELD_LIST(type) \
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type DCFE_CLOCK_ENABLE; \
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type DCFEV_CLOCK_ENABLE; \
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