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dt-bindings: interrupt-controller: sifive,plic: Clarify the riscv,ndev meaning in PLIC

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In PLIC, interrupt source 0 is reserved and should not be used.
Therefore, the valid interrupt sources are from 1 to riscv,ndev
inclusive.

Update the documentation to clarify this point.

[ tglx: Fixup subject prefix ]

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Link: https://patch.msgid.link/tencent_720A4669773B1EE15EC720869C35C2F0490A@qq.com
This commit is contained in:
Yangyu Chen
2026-02-04 01:21:48 +08:00
committed by Thomas Gleixner
parent 42e025b719
commit 889588d750
1 changed files with 3 additions and 1 deletions
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4
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
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@@ -108,7 +108,9 @@ properties:
riscv,ndev:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Specifies how many external interrupts are supported by this controller.
Specifies how many external (device) interrupts are supported by this
controller. Note that source 0 is reserved in PLIC, so the valid
interrupt sources are 1 to riscv,ndev inclusive.
clocks: true