bybrooklyn/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-04-18 14:53:58 -04:00
Code Issues Packages Projects Releases Wiki Activity

PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver

Browse Source 
Add support for Xilinx XDMA Soft IP core as Root Port.

The Zynq UltraScale+ MPSoCs devices support XDMA soft IP module in
programmable logic.

The integrated XDMA Soft IP block has integrated bridge function that
can act as PCIe Root Port.

[kwilczynski: correct indentation and whitespaces, Kconfig help update]
Link: https://lore.kernel.org/linux-pci/20231003173453.938190-4-thippeswamy.havalige@amd.com
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
This commit is contained in:
Thippeswamy Havalige
2023-10-03 23:04:53 +05:30
committed by Krzysztof Wilczyński
parent 4ae1cd7d4b
commit 8d786149d7
4 changed files with 827 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/pci/controller/Kconfig
View File

@@ -324,6 +324,17 @@ config PCIE_XILINX
Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
Host Bridge driver.
config PCIE_XILINX_DMA_PL
bool "Xilinx DMA PL PCIe host bridge support"
depends on ARCH_ZYNQMP || COMPILE_TEST
depends on PCI_MSI
select PCI_HOST_COMMON
help
Say 'Y' here if you want kernel support for the Xilinx PL DMA
PCIe host bridge. The controller is a Soft IP which can act as
Root Port. If your system provides Xilinx PCIe host controller
bridge DMA as Soft IP say 'Y'; if you are not sure, say 'N'.
config PCIE_XILINX_NWL
bool "Xilinx NWL PCIe controller"
depends on ARCH_ZYNQMP || COMPILE_TEST