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drm/i915: Move ggtt fence/alignment to i915_gem_tiling.c

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Rename i915_gem_get_ggtt_size() and i915_gem_get_ggtt_alignment() to
i915_gem_fence_size() and i915_gem_fence_alignment() respectively to
better match usage. Similarly move the pair of functions into
i915_gem_tiling.c next to the fence restrictions.

Suggested-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170109161613.11881-6-chris@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
This commit is contained in:
Chris Wilson
2017-01-09 16:16:13 +00:00
parent cea84d16c3
commit 91d4e0aa92
4 changed files with 88 additions and 88 deletions
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69
drivers/gpu/drm/i915/i915_gem.c
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@@ -2016,75 +2016,6 @@ void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
}
}
/**
* i915_gem_get_ggtt_size - return required global GTT size for an object
* @dev_priv: i915 device
* @size: object size
* @tiling_mode: tiling mode
* @stride: tiling stride
*
* Return the required global GTT size for an object, taking into account
* potential fence register mapping.
*/
u32 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv,
u32 size, int tiling_mode, unsigned int stride)
{
u32 ggtt_size;
GEM_BUG_ON(!size);
if (tiling_mode == I915_TILING_NONE)
return size;
GEM_BUG_ON(!stride);
if (INTEL_GEN(dev_priv) >= 4) {
stride *= i915_gem_tile_height(tiling_mode);
GEM_BUG_ON(stride & 4095);
return roundup(size, stride);
}
/* Previous chips need a power-of-two fence region when tiling */
if (IS_GEN3(dev_priv))
ggtt_size = 1024*1024;
else
ggtt_size = 512*1024;
while (ggtt_size < size)
ggtt_size <<= 1;
return ggtt_size;
}
/**
* i915_gem_get_ggtt_alignment - return required global GTT alignment
* @dev_priv: i915 device
* @size: object size
* @tiling_mode: tiling mode
* @stride: tiling stride
*
* Return the required global GTT alignment for an object, taking into account
* potential fence register mapping.
*/
u32 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u32 size,
int tiling_mode, unsigned int stride)
{
GEM_BUG_ON(!size);
/*
* Minimum alignment is 4k (GTT page size), but might be greater
* if a fence register is needed for the object.
*/
if (INTEL_GEN(dev_priv) >= 4 || tiling_mode == I915_TILING_NONE)
return 4096;
/*
* Previous chips need to be aligned to the size of the smallest
* fence register that can contain the object.
*/
return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode, stride);
}
static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *dev_priv = to_i915(obj->base.dev);