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drm/amd/display: Enable runtime register offset init for DCN32 DMUB

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[Why&How]
DMUB subsystem was continuing to use compile time offset calculation for
register access. Switch this to runtime calculation to stay consistent
with rest of DC code.

To enable this, an additional interface init_reg_offsets() are added to
DMUB's hw_funcs struct. Asics with runtime register offset calculation
enabled shall populate this hook with a fn pointer that will invoke the
necessary macros to calculate the offset.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Aurabindo Pillai
2023-08-08 16:25:59 -04:00
committed by Alex Deucher
parent 45f98fccb1
commit 96182df99d
5 changed files with 35 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
View File

@@ -26,33 +26,39 @@
#include "../dmub_srv.h"
#include "dmub_reg.h"
#include "dmub_dcn32.h"
#include "dc/dc_types.h"
#include "dcn/dcn_3_2_0_offset.h"
#include "dcn/dcn_3_2_0_sh_mask.h"
#define DCN_BASE__INST0_SEG2 0x000034C0
#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
#define CTX dmub
#define REGS dmub->regs_dcn32
#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
const struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs = {
#define DMUB_SR(reg) REG_OFFSET_EXP(reg),
{
DMUB_DCN32_REGS()
DMCUB_INTERNAL_REGS()
},
void dmub_srv_dcn32_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)
{
struct dmub_srv_dcn32_regs *regs = dmub->regs_dcn32;
#define REG_STRUCT regs
#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);
DMUB_DCN32_REGS()
DMCUB_INTERNAL_REGS()
#undef DMUB_SR
#define DMUB_SF(reg, field) FD_MASK(reg, field),
{ DMUB_DCN32_FIELDS() },
#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);
DMUB_DCN32_FIELDS()
#undef DMUB_SF
#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
{ DMUB_DCN32_FIELDS() },
#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);
DMUB_DCN32_FIELDS()
#undef DMUB_SF
};
#undef REG_STRUCT
}
static void dmub_dcn32_get_fb_base_offset(struct dmub_srv *dmub,
uint64_t *fb_base,

10
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h
View File

@@ -178,13 +178,11 @@ struct dmub_srv_dcn32_reg_mask {
};
struct dmub_srv_dcn32_regs {
const struct dmub_srv_dcn32_reg_offset offset;
const struct dmub_srv_dcn32_reg_mask mask;
const struct dmub_srv_dcn32_reg_shift shift;
struct dmub_srv_dcn32_reg_offset offset;
struct dmub_srv_dcn32_reg_mask mask;
struct dmub_srv_dcn32_reg_shift shift;
};
extern const struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs;
void dmub_dcn32_reset(struct dmub_srv *dmub);
void dmub_dcn32_reset_release(struct dmub_srv *dmub);
@@ -256,4 +254,6 @@ void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_re
void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub);
uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub);
void dmub_srv_dcn32_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);
#endif /* _DMUB_DCN32_H_ */

3
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
View File

@@ -78,6 +78,8 @@
#define DMUB_REGION5_BASE (0xA0000000)
static struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs;
static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
{
return (val + factor - 1) / factor * factor;
@@ -304,6 +306,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr;
funcs->get_current_time = dmub_dcn32_get_current_time;
funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data;
funcs->init_reg_offsets = dmub_srv_dcn32_regs_init;
break;