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drm/amd: GFX12 changes for converting tiling flags to modifiers
GFX12 swizzle mode and GCC formats changed and is much simpler. Use a seperate function for the same. Changes: * Swizzle mode is now 3 bits only * DCC enablement doesn't come from tiling_flags, it is always set in modifiers * DCC max compressed block size of 128B Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
committed by
Alex Deucher
parent
7d09d80b93
commit
96557f785a
@@ -718,6 +718,37 @@ extract_render_dcc_offset(struct amdgpu_device *adev,
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return 0;
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}
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static int convert_tiling_flags_to_modifier_gfx12(struct amdgpu_framebuffer *afb)
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{
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struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
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const struct drm_format_info *format_info;
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u64 modifier = 0;
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int tile = 0;
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int swizzle = 0;
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if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) {
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tile = AMD_FMT_MOD_TILE_VER_GFX12;
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swizzle = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE);
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}
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modifier =
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AMD_FMT_MOD |
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AMD_FMT_MOD_SET(TILE, swizzle) |
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AMD_FMT_MOD_SET(TILE_VERSION, tile) |
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AMD_FMT_MOD_SET(DCC, 0) |
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AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, 0);
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format_info = amdgpu_lookup_format_info(afb->base.format->format,
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modifier);
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if (!format_info)
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return -EINVAL;
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afb->base.modifier = modifier;
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afb->base.flags |= DRM_MODE_FB_MODIFIERS;
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return 0;
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}
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static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
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{
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struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
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@@ -742,6 +773,12 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
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int pipes = ilog2(num_pipes);
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uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
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if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) {
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convert_tiling_flags_to_modifier_gfx12(afb);
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return 0;
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}
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switch (swizzle >> 2) {
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case 0: /* 256B */
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block_size_bits = 8;
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