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PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

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Since commit f3ac2ff148 ("PCI/ASPM: Enable all ClockPM and ASPM states
for devicetree platforms") force enables ASPM on all device tree platforms,
the SG2042 Root Ports are breaking as they advertise L0s and L1
capabilities without supporting them.

Set ASPM quirks to disable the L0s and L1 capabilities for the Root Ports
so that these broken link states won't be enabled.

Fixes: 4e27aca488 ("riscv: sophgo: dts: add PCIe controllers for SG2042")
Co-developed-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Yao Zi <me@ziyao.cc>
[mani: commit log]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Han Gao <gaohan@iscas.ac.cn>
Tested-by: Chen Wang <unicorn_wang@outlook.com> # Pioneerbox
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://patch.msgid.link/20260405154154.46829-3-me@ziyao.cc
This commit is contained in:
Yao Zi
2026-04-05 15:41:54 +00:00
committed by Bjorn Helgaas
parent 5ccc76a87f
commit 988ef706cd
1 changed files with 2 additions and 0 deletions
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2
drivers/pci/controller/cadence/pcie-sg2042.c
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@@ -48,6 +48,8 @@ static int sg2042_pcie_probe(struct platform_device *pdev)
bridge->child_ops = &sg2042_pcie_child_ops;
rc = pci_host_bridge_priv(bridge);
rc->quirk_broken_aspm_l0s = 1;
rc->quirk_broken_aspm_l1 = 1;
pcie = &rc->pcie;
pcie->dev = dev;