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drm/amd/display: Add MPC 3DLUT resource management
[Why & How] Number of 3DLUT's in MPC are not equal to number of pipes. Resource management is required. Activate on FPGA entire tm solution which includes the following :hdr multiplier, shaper, 3dlut. Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Gary Kattan <Gary.Kattan@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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committed by
Alex Deucher
parent
70f1476a7e
commit
a208009869
@@ -616,12 +616,26 @@ struct dc_transfer_func {
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#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
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union dc_3dlut_state {
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struct {
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uint32_t initialized:1; /*if 3dlut is went through color module for initialization */
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uint32_t rmu_idx_valid:1; /*if mux settings are valid*/
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uint32_t rmu_mux_num:3; /*index of mux to use*/
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uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
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uint32_t mpc_rmu1_mux:4;
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uint32_t mpc_rmu2_mux:4;
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uint32_t reserved:15;
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} bits;
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uint32_t raw;
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};
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struct dc_3dlut {
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struct kref refcount;
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struct tetrahedral_params lut_3d;
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uint32_t hdr_multiplier;
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bool initialized;
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bool initialized; /*remove after diag fix*/
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union dc_3dlut_state state;
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struct dc_context *ctx;
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};
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#endif
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