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drm/amd/display: Add MPC 3DLUT resource management
[Why & How] Number of 3DLUT's in MPC are not equal to number of pipes. Resource management is required. Activate on FPGA entire tm solution which includes the following :hdr multiplier, shaper, 3dlut. Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Gary Kattan <Gary.Kattan@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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committed by
Alex Deucher
parent
70f1476a7e
commit
a208009869
@@ -952,14 +952,14 @@ static bool dcn20_set_shaper_3dlut(
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result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
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if (plane_state->lut3d_func &&
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plane_state->lut3d_func->initialized == true)
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plane_state->lut3d_func->state.bits.initialized == 1)
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result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
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&plane_state->lut3d_func->lut_3d);
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else
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result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
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if (plane_state->lut3d_func &&
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plane_state->lut3d_func->initialized == true &&
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plane_state->lut3d_func->state.bits.initialized == 1 &&
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plane_state->lut3d_func->hdr_multiplier != 0)
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dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base,
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plane_state->lut3d_func->hdr_multiplier);
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