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drm/amd/display: DPCD for Selective Update

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[Why&How]
Add flow to read selective update related info from DPCD,
and pass the info to DMUB.

Reviewed-by: Robin Chen <robin.chen@amd.com>
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Jack Chang <jack.chang@amd.com>
Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jack Chang
2025-12-04 16:57:47 +08:00
committed by Alex Deucher
parent ac1e65d8ad
commit a230696d4e
4 changed files with 97 additions and 4 deletions
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47
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
View File

@@ -1593,6 +1593,41 @@ static bool dpcd_read_sink_ext_caps(struct dc_link *link)
return true;
}
static void retrieve_vesa_replay_su_info(struct dc_link *link)
{
uint8_t dpcd_data = 0;
core_link_read_dpcd(link,
DP_PR_SU_X_GRANULARITY_LOW,
&dpcd_data,
sizeof(dpcd_data));
link->dpcd_caps.vesa_replay_su_info.pr_su_x_granularity = dpcd_data;
core_link_read_dpcd(link,
DP_PR_SU_X_GRANULARITY_HIGH,
&dpcd_data,
sizeof(dpcd_data));
link->dpcd_caps.vesa_replay_su_info.pr_su_x_granularity |= (dpcd_data << 8);
core_link_read_dpcd(link,
DP_PR_SU_Y_GRANULARITY,
&dpcd_data,
sizeof(dpcd_data));
link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity = dpcd_data;
core_link_read_dpcd(link,
DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW,
&dpcd_data,
sizeof(dpcd_data));
link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity_extended_caps = dpcd_data;
core_link_read_dpcd(link,
DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH,
&dpcd_data,
sizeof(dpcd_data));
link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity_extended_caps |= (dpcd_data << 8);
}
enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)
{
uint8_t lttpr_dpcd_data[10] = {0};
@@ -2094,8 +2129,16 @@ static bool retrieve_link_cap(struct dc_link *link)
core_link_read_dpcd(link,
DP_PANEL_REPLAY_CAPABILITY_SUPPORT,
&link->dpcd_caps.pr_caps_supported.raw,
sizeof(link->dpcd_caps.pr_caps_supported.raw));
&link->dpcd_caps.vesa_replay_caps_supported.raw,
sizeof(link->dpcd_caps.vesa_replay_caps_supported.raw));
core_link_read_dpcd(link,
DP_PANEL_REPLAY_CAPABILITY,
&link->dpcd_caps.vesa_replay_caps.raw,
sizeof(link->dpcd_caps.vesa_replay_caps.raw));
/* Read VESA Panel Replay Selective Update caps */
retrieve_vesa_replay_su_info(link);
/* Read DP tunneling information. */
status = dpcd_get_tunneling_device_data(link);

16
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
View File

@@ -113,7 +113,10 @@ static bool dp_setup_panel_replay(struct dc_link *link, const struct dc_stream_s
pr_config_1.bits.PANEL_REPLAY_EARLY_TRANSPORT_ENABLE = 1;
pr_config_2.bits.SINK_REFRESH_RATE_UNLOCK_GRANTED = 0;
pr_config_2.bits.SU_Y_GRANULARITY_EXT_VALUE_ENABLED = 0;
if (link->dpcd_caps.vesa_replay_caps.bits.SU_Y_GRANULARITY_EXT_CAP_SUPPORTED)
pr_config_2.bits.SU_Y_GRANULARITY_EXT_VALUE_ENABLED = 1;
pr_config_2.bits.SU_REGION_SCAN_LINE_CAPTURE_INDICATION = 0;
dm_helpers_dp_write_dpcd(link->ctx, link,
@@ -231,6 +234,17 @@ bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_con
cmd.pr_copy_settings.data.flags.bitfields.dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);
cmd.pr_copy_settings.data.debug.u32All = link->replay_settings.config.debug_flags;
cmd.pr_copy_settings.data.su_granularity_needed = link->dpcd_caps.vesa_replay_caps.bits.PR_SU_GRANULARITY_NEEDED;
cmd.pr_copy_settings.data.su_x_granularity = link->dpcd_caps.vesa_replay_su_info.pr_su_x_granularity;
cmd.pr_copy_settings.data.su_y_granularity = link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity;
cmd.pr_copy_settings.data.su_y_granularity_extended_caps =
link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity_extended_caps;
if (pipe_ctx->stream->timing.dsc_cfg.num_slices_v > 0)
cmd.pr_copy_settings.data.dsc_slice_height = (pipe_ctx->stream->timing.v_addressable +
pipe_ctx->stream->timing.v_border_top + pipe_ctx->stream->timing.v_border_bottom) /
pipe_ctx->stream->timing.dsc_cfg.num_slices_v;
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
return true;
}