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drm/amd/display: Add Support for reg inbox0 for host->DMUB CMDs

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[WHY]
DCN4+ supports a new register based mailbox for sending messages
from host to DMCUB. This mailbox supports 64 byte commands, which makes
it compatible with the same structure as the frame buffer based mailbox.

[HOW]
The intention for reg_inbox0 is to be slot in replacement for the frame
buffer based mailbox (Inbox1). It supports all of the required features:
- Supports all messages handled by FB Inbox1
- Supports multi command batching

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dillon Varone
2025-03-19 12:45:13 -04:00
committed by Alex Deucher
parent 4b884e3f03
commit a3b7dc4a1e
11 changed files with 510 additions and 280 deletions
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4
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
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@@ -5993,6 +5993,9 @@ static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb)
else
data_count = rb->capacity - (rb->rptr - rb->wrpt);
/* +1 because 1 entry is always unusable */
data_count += DMUB_RB_CMD_SIZE;
return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE;
}
@@ -6012,6 +6015,7 @@ static inline bool dmub_rb_full(struct dmub_rb *rb)
else
data_count = rb->capacity - (rb->rptr - rb->wrpt);
/* -1 because 1 entry is always unusable */
return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
}