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mips: bmips: rework and cache CBR addr handling

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Rework the handling of the CBR address and cache it. This address
doesn't change and can be cached instead of reading the register every
time.

This is in preparation of permitting to tweak the CBR address in DT with
broken SoC or bootloader.

bmips_cbr_addr is defined in setup.c for each arch to keep compatibility
with legacy brcm47xx/brcm63xx and generic BMIPS target.

Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Christian Marangi
2024-06-20 17:26:42 +02:00
committed by Thomas Bogendoerfer
parent 7c48090af5
commit a5c05453a1
8 changed files with 24 additions and 4 deletions
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4
arch/mips/bcm47xx/setup.c
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@@ -37,6 +37,7 @@
#include <linux/ssb/ssb.h>
#include <linux/ssb/ssb_embedded.h>
#include <linux/bcma/bcma_soc.h>
#include <asm/bmips.h>
#include <asm/bootinfo.h>
#include <asm/idle.h>
#include <asm/prom.h>
@@ -45,6 +46,9 @@
#include <bcm47xx.h>
#include <bcm47xx_board.h>
/* CBR addr doesn't change and we can cache it */
void __iomem *bmips_cbr_addr __read_mostly;
union bcm47xx_bus bcm47xx_bus;
EXPORT_SYMBOL(bcm47xx_bus);