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drm/msm: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
@@ -8,9 +8,17 @@ http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml ( 29312 bytes, from 2015-03-23 21:18:48)
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- /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2014-06-02 18:31:15)
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- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2015-03-23 20:38:49)
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- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
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- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
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- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
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- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
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- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
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- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
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- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
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- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
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- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
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Copyright (C) 2013-2015 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@@ -120,6 +128,21 @@ enum mdp5_data_format {
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DATA_FORMAT_YUV = 1,
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};
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enum mdp5_block_size {
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BLOCK_SIZE_64 = 0,
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BLOCK_SIZE_128 = 1,
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};
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enum mdp5_rotate_mode {
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ROTATE_0 = 0,
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ROTATE_90 = 1,
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};
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enum mdp5_chroma_downsample_method {
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DS_MTHD_NO_PIXEL_DROP = 0,
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DS_MTHD_PIXEL_DROP = 1,
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};
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#define MDP5_IRQ_WB_0_DONE 0x00000001
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#define MDP5_IRQ_WB_1_DONE 0x00000002
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#define MDP5_IRQ_WB_2_DONE 0x00000010
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@@ -314,19 +337,19 @@ static inline uint32_t MDP5_MDP_IGC_LUT_REG_VAL(uint32_t val)
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#define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000
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#define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000
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#define REG_MDP5_SPLIT_DPL_EN 0x000003f4
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static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_EN(uint32_t i0) { return 0x000002f4 + __offset_MDP(i0); }
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#define REG_MDP5_SPLIT_DPL_UPPER 0x000003f8
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#define MDP5_SPLIT_DPL_UPPER_SMART_PANEL 0x00000002
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#define MDP5_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN 0x00000004
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#define MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX 0x00000010
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#define MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX 0x00000100
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static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_UPPER(uint32_t i0) { return 0x000002f8 + __offset_MDP(i0); }
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#define MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL 0x00000002
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#define MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN 0x00000004
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#define MDP5_MDP_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX 0x00000010
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#define MDP5_MDP_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX 0x00000100
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#define REG_MDP5_SPLIT_DPL_LOWER 0x000004f0
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#define MDP5_SPLIT_DPL_LOWER_SMART_PANEL 0x00000002
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#define MDP5_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN 0x00000004
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#define MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC 0x00000010
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#define MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC 0x00000100
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static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_LOWER(uint32_t i0) { return 0x000003f0 + __offset_MDP(i0); }
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#define MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL 0x00000002
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#define MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN 0x00000004
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#define MDP5_MDP_SPLIT_DPL_LOWER_INTF1_TG_SYNC 0x00000010
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#define MDP5_MDP_SPLIT_DPL_LOWER_INTF2_TG_SYNC 0x00000100
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static inline uint32_t __offset_CTL(uint32_t idx)
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{
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@@ -782,7 +805,7 @@ static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
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#define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
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#define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK 0x00180000
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#define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT 19
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static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(enum mdp_sspp_fetch_type val)
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static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(enum mdp_fetch_type val)
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{
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return ((val) << MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT) & MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK;
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}
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@@ -1234,6 +1257,351 @@ static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x000000
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static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0); }
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static inline uint32_t __offset_WB(uint32_t idx)
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{
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switch (idx) {
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default: return INVALID_IDX(idx);
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}
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}
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static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
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static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
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#define MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK 0x00000003
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#define MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT 0
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static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK;
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}
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#define MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK 0x0000000c
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#define MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT 2
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static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK;
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}
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#define MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK 0x00000030
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#define MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT 4
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static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK;
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}
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#define MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK 0x000000c0
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#define MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT 6
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static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK;
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}
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#define MDP5_WB_DST_FORMAT_DSTC3_EN 0x00000100
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#define MDP5_WB_DST_FORMAT_DST_BPP__MASK 0x00000600
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#define MDP5_WB_DST_FORMAT_DST_BPP__SHIFT 9
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static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_FORMAT_DST_BPP__SHIFT) & MDP5_WB_DST_FORMAT_DST_BPP__MASK;
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}
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#define MDP5_WB_DST_FORMAT_PACK_COUNT__MASK 0x00003000
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#define MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT 12
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static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT) & MDP5_WB_DST_FORMAT_PACK_COUNT__MASK;
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}
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#define MDP5_WB_DST_FORMAT_DST_ALPHA_X 0x00004000
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#define MDP5_WB_DST_FORMAT_PACK_TIGHT 0x00020000
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#define MDP5_WB_DST_FORMAT_PACK_ALIGN_MSB 0x00040000
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#define MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK 0x00180000
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#define MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT 19
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static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT) & MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK;
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}
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#define MDP5_WB_DST_FORMAT_DST_DITHER_EN 0x00400000
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#define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK 0x03800000
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#define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT 23
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static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK;
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}
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#define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK 0x3c000000
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#define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT 26
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static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK;
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}
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#define MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK 0xc0000000
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#define MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT 30
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static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT) & MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK;
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}
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static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); }
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#define MDP5_WB_DST_OP_MODE_BWC_ENC_EN 0x00000001
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#define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK 0x00000006
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#define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT 1
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static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT) & MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK;
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}
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#define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK 0x00000010
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#define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT 4
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static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT) & MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK;
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}
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#define MDP5_WB_DST_OP_MODE_ROT_MODE__MASK 0x00000020
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#define MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT 5
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static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT) & MDP5_WB_DST_OP_MODE_ROT_MODE__MASK;
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}
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#define MDP5_WB_DST_OP_MODE_ROT_EN 0x00000040
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#define MDP5_WB_DST_OP_MODE_CSC_EN 0x00000100
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#define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00000200
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#define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 9
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static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
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}
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#define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00000400
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#define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 10
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static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
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}
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#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_EN 0x00000800
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#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK 0x00001000
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#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT 12
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static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK;
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}
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#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK 0x00002000
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#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT 13
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static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK;
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}
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#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK 0x00004000
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#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT 14
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static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK;
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}
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static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0); }
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#define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK 0x00000003
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#define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT 0
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static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK;
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}
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#define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK 0x00000300
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#define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT 8
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static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK;
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}
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#define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK 0x00030000
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#define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT 16
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static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK;
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}
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#define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK 0x03000000
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#define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT 24
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static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK;
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}
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static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); }
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static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); }
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static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); }
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static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); }
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static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0); }
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#define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK 0x0000ffff
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#define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT 0
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static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val)
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{
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return ((val) << MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK;
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}
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||||
#define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK 0xffff0000
|
||||
#define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT 16
|
||||
static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0); }
|
||||
#define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK 0x0000ffff
|
||||
#define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT 0
|
||||
static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK;
|
||||
}
|
||||
#define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK 0xffff0000
|
||||
#define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT 16
|
||||
static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0); }
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0); }
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0); }
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0); }
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0); }
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0); }
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0); }
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0); }
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0); }
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0); }
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0); }
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); }
|
||||
#define MDP5_WB_OUT_SIZE_DST_W__MASK 0x0000ffff
|
||||
#define MDP5_WB_OUT_SIZE_DST_W__SHIFT 0
|
||||
static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_OUT_SIZE_DST_W__SHIFT) & MDP5_WB_OUT_SIZE_DST_W__MASK;
|
||||
}
|
||||
#define MDP5_WB_OUT_SIZE_DST_H__MASK 0xffff0000
|
||||
#define MDP5_WB_OUT_SIZE_DST_H__SHIFT 16
|
||||
static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_OUT_SIZE_DST_H__SHIFT) & MDP5_WB_OUT_SIZE_DST_H__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0); }
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0); }
|
||||
#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff
|
||||
#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT 0
|
||||
static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK;
|
||||
}
|
||||
#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000
|
||||
#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT 16
|
||||
static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0); }
|
||||
#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff
|
||||
#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT 0
|
||||
static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK;
|
||||
}
|
||||
#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000
|
||||
#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT 16
|
||||
static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0); }
|
||||
#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff
|
||||
#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT 0
|
||||
static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK;
|
||||
}
|
||||
#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000
|
||||
#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT 16
|
||||
static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0); }
|
||||
#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff
|
||||
#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT 0
|
||||
static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK;
|
||||
}
|
||||
#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000
|
||||
#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT 16
|
||||
static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0); }
|
||||
#define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff
|
||||
#define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT 0
|
||||
static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
|
||||
#define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK 0x000000ff
|
||||
#define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT 0
|
||||
static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK;
|
||||
}
|
||||
#define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK 0x0000ff00
|
||||
#define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT 8
|
||||
static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
|
||||
#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK 0x000000ff
|
||||
#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT 0
|
||||
static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK;
|
||||
}
|
||||
#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK 0x0000ff00
|
||||
#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT 8
|
||||
static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
|
||||
#define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK 0x000001ff
|
||||
#define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT 0
|
||||
static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
|
||||
|
||||
static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
|
||||
#define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK 0x000001ff
|
||||
#define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT 0
|
||||
static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val)
|
||||
{
|
||||
return ((val) << MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t __offset_INTF(uint32_t idx)
|
||||
{
|
||||
switch (idx) {
|
||||
|
||||
Reference in New Issue
Block a user