riscv: Add tests for riscv module loading

Add test cases for the two main groups of relocations added: SUB and
SET, along with uleb128.

Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Link: https://lore.kernel.org/r/20231101-module_relocations-v9-3-8dfa3483c400@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Charlie Jenkins
2023-11-01 11:33:01 -07:00
committed by Palmer Dabbelt
parent 8fd6c51423
commit af71bc1949
16 changed files with 366 additions and 0 deletions

View File

@@ -0,0 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2023 Rivos Inc.
*/
.text
.global test_set8
test_set8:
lw a0, set8
la t0, set8
#ifdef CONFIG_32BIT
slli t0, t0, 24
srli t0, t0, 24
#else
slli t0, t0, 56
srli t0, t0, 56
#endif
sub a0, a0, t0
ret
.data
set8:
.reloc set8, R_RISCV_SET8, set8
.word 0