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drm/amd/display: Re-add aux intercept disable delay generically for 2+ LTTPRs

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[WHY]
Issue not display generic, required for multiple 2+ LTTPR link configurations.

[HOW]
Revert monitor patch change and remove delay for single LTTPR case

Reviewed-by: George Shen <george.shen@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Michael Strauss
2023-06-12 10:27:09 -04:00
committed by Alex Deucher
parent ac30aeae7a
commit c4e532f753
3 changed files with 13 additions and 14 deletions
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25
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c
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@@ -244,10 +244,6 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence_legacy(
uint8_t toggle_rate;
uint8_t rate;
if (link->local_sink)
pre_disable_intercept_delay_ms =
link->local_sink->edid_caps.panel_patch.delay_disable_aux_intercept_ms;
/* Only 8b/10b is supported */
ASSERT(link_dp_get_encoding_format(&lt_settings->link_settings) ==
DP_8b_10b_ENCODING);
@@ -260,10 +256,13 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence_legacy(
if (offset != 0xFF) {
vendor_lttpr_write_address +=
((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
if (offset == 2) {
pre_disable_intercept_delay_ms = link->dc->debug.fixed_vs_aux_delay_config_wa;
/* Certain display and cable configuration require extra delay */
if (offset > 2)
pre_disable_intercept_delay_ms = pre_disable_intercept_delay_ms * 2;
} else if (offset > 2) {
pre_disable_intercept_delay_ms = link->dc->debug.fixed_vs_aux_delay_config_wa * 2;
}
}
/* Vendor specific: Reset lane settings */
@@ -596,9 +595,10 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
const uint8_t vendor_lttpr_write_data_adicora_eq1[4] = {0x1, 0x55, 0x63, 0x2E};
const uint8_t vendor_lttpr_write_data_adicora_eq2[4] = {0x1, 0x55, 0x63, 0x01};
const uint8_t vendor_lttpr_write_data_adicora_eq3[4] = {0x1, 0x55, 0x63, 0x68};
uint32_t pre_disable_intercept_delay_ms = 0;
uint8_t vendor_lttpr_write_data_vs[4] = {0x1, 0x51, 0x63, 0x0};
uint8_t vendor_lttpr_write_data_pe[4] = {0x1, 0x52, 0x63, 0x0};
uint32_t pre_disable_intercept_delay_ms = 0;
uint32_t vendor_lttpr_write_address = 0xF004F;
enum link_training_result status = LINK_TRAINING_SUCCESS;
uint8_t lane = 0;
@@ -607,10 +607,6 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
uint8_t toggle_rate;
uint8_t rate;
if (link->local_sink)
pre_disable_intercept_delay_ms =
link->local_sink->edid_caps.panel_patch.delay_disable_aux_intercept_ms;
/* Only 8b/10b is supported */
ASSERT(link_dp_get_encoding_format(&lt_settings->link_settings) ==
DP_8b_10b_ENCODING);
@@ -623,10 +619,13 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
if (offset != 0xFF) {
vendor_lttpr_write_address +=
((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
if (offset == 2) {
pre_disable_intercept_delay_ms = link->dc->debug.fixed_vs_aux_delay_config_wa;
/* Certain display and cable configuration require extra delay */
if (offset > 2)
pre_disable_intercept_delay_ms = pre_disable_intercept_delay_ms * 2;
} else if (offset > 2) {
pre_disable_intercept_delay_ms = link->dc->debug.fixed_vs_aux_delay_config_wa * 2;
}
}
/* Vendor specific: Reset lane settings */