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clk: at91: sam9x7: update pll clk ranges

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Update the min, max ranges of the PLL clocks according to the latest
datasheet to be coherent in the driver. This patch solves the issues in
configuring the clocks related to peripherals with the desired frequency
within the range.

Fixes: 33013b43e2 ("clk: at91: sam9x7: add sam9x7 pmc driver")
Suggested-by: Patrice Vilchez <Patrice.Vilchez@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Link: https://lore.kernel.org/r/20250714093512.29944-1-varshini.rajendran@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
This commit is contained in:
Varshini Rajendran
2025-07-14 15:05:12 +05:30
committed by Claudiu Beznea
parent 19272b37aa
commit c7f7ddbd27
1 changed files with 10 additions and 10 deletions
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20
drivers/clk/at91/sam9x7.c
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@@ -61,44 +61,44 @@ static const struct clk_master_layout sam9x7_master_layout = {
/* Fractional PLL core output range. */
static const struct clk_range plla_core_outputs[] = {
{ .min = 375000000, .max = 1600000000 },
{ .min = 800000000, .max = 1600000000 },
};
static const struct clk_range upll_core_outputs[] = {
{ .min = 600000000, .max = 1200000000 },
{ .min = 600000000, .max = 960000000 },
};
static const struct clk_range lvdspll_core_outputs[] = {
{ .min = 400000000, .max = 800000000 },
{ .min = 600000000, .max = 1200000000 },
};
static const struct clk_range audiopll_core_outputs[] = {
{ .min = 400000000, .max = 800000000 },
{ .min = 600000000, .max = 1200000000 },
};
static const struct clk_range plladiv2_core_outputs[] = {
{ .min = 375000000, .max = 1600000000 },
{ .min = 800000000, .max = 1600000000 },
};
/* Fractional PLL output range. */
static const struct clk_range plla_outputs[] = {
{ .min = 732421, .max = 800000000 },
{ .min = 400000000, .max = 800000000 },
};
static const struct clk_range upll_outputs[] = {
{ .min = 300000000, .max = 600000000 },
{ .min = 300000000, .max = 480000000 },
};
static const struct clk_range lvdspll_outputs[] = {
{ .min = 10000000, .max = 800000000 },
{ .min = 175000000, .max = 550000000 },
};
static const struct clk_range audiopll_outputs[] = {
{ .min = 10000000, .max = 800000000 },
{ .min = 0, .max = 300000000 },
};
static const struct clk_range plladiv2_outputs[] = {
{ .min = 366210, .max = 400000000 },
{ .min = 200000000, .max = 400000000 },
};
/* PLL characteristics. */