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KVM: arm64: GICv3: Handle deactivation via ICV_DIR_EL1 traps
Deactivation via ICV_DIR_EL1 is both relatively straightforward (we have the interrupt that needs deactivation) and really awkward. The main issue is that the interrupt may either be in an LR on another CPU, or ourside of any LR. In the former case, we process the deactivation is if ot was a write to GICD_CACTIVERn, which is already implemented as a big hammer IPI'ing all vcpus. In the latter case, we just perform a normal deactivation, similar to what we do for EOImode==0. Another annoying aspect is that we need to tell the CPU owning the interrupt that its ap_list needs laudering. We use a brand new vcpu request to that effect. Note that this doesn't address deactivation via the GICV MMIO view, which will be taken care of in a later change. Tested-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Mark Brown <broonie@kernel.org> Link: https://msgid.link/20251120172540.2267180-29-maz@kernel.org Signed-off-by: Oliver Upton <oupton@kernel.org>
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Oliver Upton
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@@ -54,6 +54,7 @@
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#define KVM_REQ_NESTED_S2_UNMAP KVM_ARCH_REQ(8)
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#define KVM_REQ_GUEST_HYP_IRQ_PENDING KVM_ARCH_REQ(9)
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#define KVM_REQ_MAP_L1_VNCR_EL2 KVM_ARCH_REQ(10)
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#define KVM_REQ_VGIC_PROCESS_UPDATE KVM_ARCH_REQ(11)
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#define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
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KVM_DIRTY_LOG_INITIALLY_SET)
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