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drm/amdgpu/mes: add multi-xcc support

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a. extend mes pipe instances to num_xcc * max_mes_pipe
b. initialize mes schq/kiq pipes per xcc
c. submit mes packet to mes ring according to xcc_id

v2: rebase (Alex)

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jack Xiao
2024-11-21 16:22:38 +08:00
committed by Alex Deucher
parent 2718942f48
commit d09c7e266c
13 changed files with 158 additions and 108 deletions
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14
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
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@@ -511,7 +511,7 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id)
j = i + xcc_id * adev->gfx.num_compute_rings;
amdgpu_mes_unmap_legacy_queue(adev,
&adev->gfx.compute_ring[j],
RESET_QUEUES, 0, 0);
RESET_QUEUES, 0, 0, xcc_id);
}
return 0;
}
@@ -562,7 +562,7 @@ int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id)
j = i + xcc_id * adev->gfx.num_gfx_rings;
amdgpu_mes_unmap_legacy_queue(adev,
&adev->gfx.gfx_ring[j],
PREEMPT_QUEUES, 0, 0);
PREEMPT_QUEUES, 0, 0, xcc_id);
}
}
return 0;
@@ -644,7 +644,8 @@ static int amdgpu_gfx_mes_enable_kcq(struct amdgpu_device *adev, int xcc_id)
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
j = i + xcc_id * adev->gfx.num_compute_rings;
r = amdgpu_mes_map_legacy_queue(adev,
&adev->gfx.compute_ring[j]);
&adev->gfx.compute_ring[j],
xcc_id);
if (r) {
dev_err(adev->dev, "failed to map compute queue\n");
return r;
@@ -733,7 +734,8 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id)
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
j = i + xcc_id * adev->gfx.num_gfx_rings;
r = amdgpu_mes_map_legacy_queue(adev,
&adev->gfx.gfx_ring[j]);
&adev->gfx.gfx_ring[j],
xcc_id);
if (r) {
dev_err(adev->dev, "failed to map gfx queue\n");
return r;
@@ -1067,7 +1069,7 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_
return 0;
if (adev->mes.ring[0].sched.ready)
return amdgpu_mes_rreg(adev, reg);
return amdgpu_mes_rreg(adev, reg, xcc_id);
BUG_ON(!ring->funcs->emit_rreg);
@@ -1143,7 +1145,7 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint3
return;
if (adev->mes.ring[0].sched.ready) {
amdgpu_mes_wreg(adev, reg, v);
amdgpu_mes_wreg(adev, reg, v, xcc_id);
return;
}