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Merge tag 'drm-next-2024-05-15' of https://gitlab.freedesktop.org/drm/kernel
Pull drm updates from Dave Airlie:
"This is the main pull request for the drm subsystems for 6.10.
In drivers the main thing is a new driver for ARM Mali firmware based
GPUs, otherwise there are a lot of changes to amdgpu/xe/i915/msm and
scattered changes to everything else.
In the core a bunch of headers and Kconfig was refactored, along with
the addition of a new panic handler which is meant to provide a user
friendly message when a panic happens and graphical display is
enabled.
New drivers:
- panthor: ARM Mali/Immortalis CSF-based GPU driver
Core:
- add a CONFIG_DRM_WERROR option
- make more headers self-contained
- grab resv lock in pin/unpin
- fix vmap resv locking
- EDID/eDP panel matching
- Kconfig cleanups
- DT sound bindings
- Add SIZE_HINTS property for cursor planes
- Add struct drm_edid_product_id and helpers.
- Use drm device based logging in more drm functions.
- drop seq_file.h from a bunch of places
- use drm_edid driver conversions
dp:
- DP Tunnel documentation
- MST read sideband cap
- Adaptive sync SDP prep work
ttm:
- improve placement for TTM BOs in idle/busy handling
panic:
- Fixes for drm-panic, and option to test it.
- Add drm panic to simpledrm, mgag200, imx, ast
bridge:
- improve init ordering
- adv7511: allow GPIO pin sharing
- tc358775: add tc358675 support
panel:
- AUO B120XAN01.0
- Samsung s6e3fa7
- BOE NT116WHM-N44
- CMN N116BCA-EA1,
- CrystalClear CMT430B19N00
- Startek KD050HDFIA020-C020A
- powertip PH128800T006-ZHC01
- Innolux G121X1-L03
- LG sw43408
- Khadas TS050 V2
- EDO RM69380 OLED
- CSOT MNB601LS1-1
amdgpu:
- HDCP/ODM/RAS fixes
- Devcoredump improvements
- Expose VCN activity via sysfs
- SMY 13.0.x updates
- Enable fast updates on DCN 3.1.4
- Add dclk and vclk reporting on additional devices
- Add ACA RAS infrastructure
- Implement TLB flush fence
- EEPROM handling fixes
- SMUIO 14.0.2 support
- SMU 14.0.1 Updates
- SMU 14.0.2 support
- Sync page table freeing with TLB flushes
- DML2 refactor
- DC debug improvements
- DCN 3.5.x Updates
- GPU reset fixes
- HDP fix for second GFX pipe on GC 10.x
- Enable secondary GFX pipe on GC 10.3
- Refactor and clean up BACO/BOCO/BAMACO handling
- Remove invalid TTM resource start check
- UAF fix in VA IOCTL
- GPUVM page fault redirection to secondary IH rings for IH 6.x
- Initial support for mapping kernel queues via MES
- Fix VRAM memory accounting
amdkfd:
- MQD handling cleanup
- Preemption handling fixes for XCDs
- TLB flush fix for GC 9.4.2
- Properly clean up workqueue during module unload
- Fix memory leak process create failure
- Range check CP bad op exception targets to avoid reporting invalid exceptions to userspace
- Fix eviction fence handling
- Fix leak in GPU memory allocation failure case
- DMABuf import handling fix
- Enable SQ watchpoint for gfx10
i915:
- Adding new DG2 PCI ID
- add context hints for GT frequency
- enable only one CCS for compute workloads
- new workarounds
- Fix UAF on destroy against retire race and remove two earlier partial fixes
- Limit the reserved VM space to only the platforms that need it
- Fix gt reset with GuC submission is disable
- Add and use gt_to_guc() wrapper
i915/xe display:
- Lunar Lake display enabling, including cdclk and other refactors
- BIOS/VBT/opregion related refactor
- Digital port related refactor/clean-up
- Fix 2s boot time regression on DP panel replay init
- Remove duplication on audio enable/disable on SDVO and g4x+ DP
- Disable AuxCCS framebuffers if built for Xe
- Make crtc disable more atomic
- Increase DP idle pattern wait timeout to 2ms
- Start using container_of_const() for some extra const safety
- Fix Jasper Lake boot freeze
- Enable MST mode for 128b/132b single-stream sideband
- Enable Adaptive Sync SDP Support for DP
- Fix MTL supported DP rates - removal of UHBR13.5
- PLL refactoring
- Limit eDP MSO pipe only for display version 20
- More display refactor towards independence from i915 dev_priv
- Convert i915/xe fbdev to DRM client
- More initial work to make display code more independent from i915
xe:
- improved error capture
- clean up some uAPI leftovers
- devcoredump update
- Add BMG mocs table
- Handle GSCCS ER interrupt
- Implement xe2- and GuC workarounds
- struct xe_device cleanup
- Hwmon updates
- Add LRC parsing for more GPU instruction
- Increase VM_BIND number of per-ioctl Ops
- drm/xe: Add XE_BO_GGTT_INVALIDATE flag
- Initial development for SR-IOV support
- Add new PCI IDs to DG2 platform
- Move userptr over to start using hmm_range_fault
msm:
- Switched to generating register header files during build process
instead of shipping pre-generated headers
- Merged DPU and MDP4 format databases.
- DP:
- Stop using compat string to distinguish DP and eDP cases
- Added support for X Elite platform (X1E80100)
- Reworked DP aux/audio support
- Added SM6350 DP to the bindings
- GPU:
- a7xx perfcntr reg fixes
- MAINTAINERS updates
- a750 devcoredump support
radeon:
- Silence UBSAN warnings related to flexible arrays
nouveau:
- move some uAPI objects to uapi headers
omapdrm:
- console fix
ast:
- add i2c polling
qaic:
- add debugfs entries
exynos:
- fix platform_driver .owner
- drop cleanup code
mediatek:
- Use devm_platform_get_and_ioremap_resource() in mtk_hdmi_ddc_probe()
- Add GAMMA 12-bit LUT support for MT8188
- Rename mtk_drm_* to mtk_*
- Drop driver owner initialization
- Correct calculation formula of PHY Timing"
* tag 'drm-next-2024-05-15' of https://gitlab.freedesktop.org/drm/kernel: (1477 commits)
drm/xe/ads: Use flexible-array
drm/xe: Use ordered WQ for G2H handler
drm/msm/gen_header: allow skipping the validation
drm/msm/a6xx: Cleanup indexed regs const'ness
drm/msm: Add devcoredump support for a750
drm/msm: Adjust a7xx GBIF debugbus dumping
drm/msm: Update a6xx registers XML
drm/msm: Fix imported a750 snapshot header for upstream
drm/msm: Import a750 snapshot registers from kgsl
MAINTAINERS: Add Konrad Dybcio as a reviewer for the Adreno driver
MAINTAINERS: Add a separate entry for Qualcomm Adreno GPU drivers
drm/msm/a6xx: Avoid a nullptr dereference when speedbin setting fails
drm/msm/adreno: fix CP cycles stat retrieval on a7xx
drm/msm/a7xx: allow writing to CP_BV counter selection registers
drm: zynqmp_dpsub: Always register bridge
Revert "drm/bridge: ti-sn65dsi83: Fix enable error path"
drm/fb_dma: Add checks in drm_fb_dma_get_scanout_buffer()
drm/fbdev-generic: Do not set physical framebuffer address
drm/panthor: Fix the FW reset logic
drm/panthor: Make sure we handle 'unknown group state' case properly
...
This commit is contained in:
Linus Torvalds
@@ -274,7 +274,7 @@ static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
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static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
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u32 *vbl, u32 *position)
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{
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u32 v_blank_start, v_blank_end, h_position, v_position;
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u32 v_blank_start = 0, v_blank_end = 0, h_position = 0, v_position = 0;
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struct amdgpu_crtc *acrtc = NULL;
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struct dc *dc = adev->dm.dc;
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@@ -848,7 +848,7 @@ static void dm_handle_hpd_work(struct work_struct *work)
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*/
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static void dm_dmub_outbox1_low_irq(void *interrupt_params)
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{
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struct dmub_notification notify;
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struct dmub_notification notify = {0};
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struct common_irq_params *irq_params = interrupt_params;
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struct amdgpu_device *adev = irq_params->adev;
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struct amdgpu_display_manager *dm = &adev->dm;
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@@ -1230,6 +1230,15 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
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break;
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}
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switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
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case IP_VERSION(3, 5, 0):
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case IP_VERSION(3, 5, 1):
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hw_params.ips_sequential_ono = adev->external_rev_id > 0x10;
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break;
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default:
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break;
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}
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status = dmub_srv_hw_init(dmub_srv, &hw_params);
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if (status != DMUB_STATUS_OK) {
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DRM_ERROR("Error initializing DMUB HW: %d\n", status);
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@@ -1726,8 +1735,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
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if (amdgpu_dc_debug_mask & DC_DISABLE_IPS)
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init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL;
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else
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init_data.flags.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
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init_data.flags.disable_ips_in_vpb = 1;
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init_data.flags.disable_ips_in_vpb = 0;
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/* Enable DWB for tested platforms only */
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if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0))
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@@ -2629,6 +2640,7 @@ static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
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int i;
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struct dc_stream_state *del_streams[MAX_PIPES];
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int del_streams_count = 0;
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struct dc_commit_streams_params params = {};
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memset(del_streams, 0, sizeof(del_streams));
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@@ -2655,7 +2667,9 @@ static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
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goto fail;
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}
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res = dc_commit_streams(dc, context->streams, context->stream_count);
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params.streams = context->streams;
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params.stream_count = context->stream_count;
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res = dc_commit_streams(dc, ¶ms);
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fail:
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dc_state_release(context);
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@@ -2877,6 +2891,7 @@ static int dm_resume(void *handle)
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struct dc_state *dc_state;
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int i, r, j, ret;
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bool need_hotplug = false;
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struct dc_commit_streams_params commit_params = {};
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if (dm->dc->caps.ips_support) {
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dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false);
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@@ -2926,7 +2941,9 @@ static int dm_resume(void *handle)
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dc_enable_dmub_outbox(adev->dm.dc);
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}
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WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
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commit_params.streams = dc_state->streams;
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commit_params.stream_count = dc_state->stream_count;
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WARN_ON(!dc_commit_streams(dm->dc, &commit_params));
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dm_gpureset_commit_state(dm->cached_dc_state, dm);
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@@ -2943,7 +2960,7 @@ static int dm_resume(void *handle)
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}
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/* Recreate dc_state - DC invalidates it when setting power state to S3. */
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dc_state_release(dm_state->context);
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dm_state->context = dc_state_create(dm->dc);
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dm_state->context = dc_state_create(dm->dc, NULL);
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/* TODO: Remove dc_state->dccg, use dc->dccg directly. */
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/* Before powering on DC we need to re-initialize DMUB. */
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@@ -3104,6 +3121,8 @@ static const struct amd_ip_funcs amdgpu_dm_funcs = {
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.soft_reset = dm_soft_reset,
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.set_clockgating_state = dm_set_clockgating_state,
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.set_powergating_state = dm_set_powergating_state,
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.dump_ip_state = NULL,
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.print_ip_state = NULL,
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};
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const struct amdgpu_ip_block_version dm_ip_block = {
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@@ -5713,8 +5732,8 @@ static void fill_stream_properties_from_drm_display_mode(
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timing_out->aspect_ratio = get_aspect_ratio(mode_in);
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stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
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stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
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stream->out_transfer_func.type = TF_TYPE_PREDEFINED;
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stream->out_transfer_func.tf = TRANSFER_FUNCTION_SRGB;
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if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
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if (!adjust_colour_depth_from_display_info(timing_out, info) &&
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drm_mode_is_420_also(info, mode_in) &&
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@@ -6332,7 +6351,7 @@ create_stream_for_sink(struct drm_connector *connector,
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stream->use_vsc_sdp_for_colorimetry = stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 &&
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stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED;
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if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
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if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22)
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tf = TRANSFER_FUNC_GAMMA_22;
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mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
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aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
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@@ -6803,7 +6822,7 @@ static enum dc_status dm_validate_stream_and_context(struct dc *dc,
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if (!dc_plane_state)
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goto cleanup;
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dc_state = dc_state_create(dc);
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dc_state = dc_state_create(dc, NULL);
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if (!dc_state)
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goto cleanup;
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@@ -7192,7 +7211,7 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
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struct amdgpu_dm_connector *aconnector;
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struct dm_connector_state *dm_conn_state;
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int i, j, ret;
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int vcpi, pbn_div, pbn, slot_num = 0;
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int vcpi, pbn_div, pbn = 0, slot_num = 0;
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for_each_new_connector_in_state(state, connector, new_con_state, i) {
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@@ -8405,13 +8424,13 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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bundle->surface_updates[planes_count].surface = dc_plane;
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if (new_pcrtc_state->color_mgmt_changed) {
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bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
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bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
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bundle->surface_updates[planes_count].gamma = &dc_plane->gamma_correction;
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bundle->surface_updates[planes_count].in_transfer_func = &dc_plane->in_transfer_func;
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bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
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bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult;
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bundle->surface_updates[planes_count].func_shaper = dc_plane->in_shaper_func;
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bundle->surface_updates[planes_count].lut3d_func = dc_plane->lut3d_func;
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bundle->surface_updates[planes_count].blend_tf = dc_plane->blend_tf;
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bundle->surface_updates[planes_count].func_shaper = &dc_plane->in_shaper_func;
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bundle->surface_updates[planes_count].lut3d_func = &dc_plane->lut3d_func;
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bundle->surface_updates[planes_count].blend_tf = &dc_plane->blend_tf;
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}
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amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
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@@ -8624,7 +8643,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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bundle->stream_update.output_csc_transform =
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&acrtc_state->stream->csc_color_matrix;
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bundle->stream_update.out_transfer_func =
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acrtc_state->stream->out_transfer_func;
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&acrtc_state->stream->out_transfer_func;
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bundle->stream_update.lut3d_func =
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(struct dc_3dlut *) acrtc_state->stream->lut3d_func;
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bundle->stream_update.func_shaper =
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@@ -8858,6 +8877,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
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struct drm_connector *connector;
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bool mode_set_reset_required = false;
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u32 i;
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struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count};
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/* Disable writeback */
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for_each_old_connector_in_state(state, connector, old_con_state, i) {
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@@ -8994,7 +9014,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
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dm_enable_per_frame_crtc_master_sync(dc_state);
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mutex_lock(&dm->dc_lock);
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WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
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WARN_ON(!dc_commit_streams(dm->dc, ¶ms));
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/* Allow idle optimization when vblank count is 0 for display off */
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if (dm->active_vblank_irq_count == 0)
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@@ -10598,7 +10618,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
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struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
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struct drm_dp_mst_topology_mgr *mgr;
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struct drm_dp_mst_topology_state *mst_state;
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struct dsc_mst_fairness_vars vars[MAX_PIPES];
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struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0};
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trace_amdgpu_dm_atomic_check_begin(state);
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