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Merge tag 'irq-drivers-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

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Pull irq chip driver updates from Thomas Gleixner:

 - Add support for the Renesas RZ/V2N SoC

 - Add a new driver for the Renesas RZ/[TN]2H SoCs

 - Preserve the register state of the RISCV APLIC interrupt controller
   accross suspend/resume

 - Reinitialize the RISCV IMSIC registers after suspend/resume

 - Make the various Loongson interrupt chip drivers 32/64-bit aware

 - Handle the number of hardware interrupts in the SIFIVE PLIC driver
   correctly

   The hardware interrupt 0 is reserved which resulted in inconsistent
   accounting. That went unnoticed as the off by one is only noticable
   when the number of device interrupts is a multiple of 32

 - The usual device tree updates, cleanups and improvements all over the
   place

* tag 'irq-drivers-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (24 commits)
  irqchip/gic-v5: Fix spelling mistake "ouside" -> "outside"
  dt-bindings: interrupt-controller: sifive,plic: Clarify the riscv,ndev meaning in PLIC
  irqchip/sifive-plic: Handle number of hardware interrupts correctly
  irqchip/aspeed-scu-ic: Remove unused variable mask
  irqchip/ti-sci-intr: Allow parsing interrupt-types per-line
  dt-bindings: interrupt-controller: ti,sci-intr: Per-line interrupt-types
  irqchip/renesas-rzv2h: Add suspend/resume support
  irqchip/aslint-sswi: Fix error check of of_io_request_and_map() result
  irqchip: Allow LoongArch irqchip drivers on both 32BIT/64BIT
  irqchip/loongson-pch-pic: Adjust irqchip driver for 32BIT/64BIT
  irqchip/loongson-pch-msi: Adjust irqchip driver for 32BIT/64BIT
  irqchip/loongson-htvec: Adjust irqchip driver for 32BIT/64BIT
  irqchip/loongson-eiointc: Adjust irqchip driver for 32BIT/64BIT
  irqchip/loongson-liointc: Adjust irqchip driver for 32BIT/64BIT
  irqchip/loongarch-avec: Adjust irqchip driver for 32BIT/64BIT
  irqchip/riscv-aplic: Preserve APLIC states across suspend/resume
  irqchip/riscv-imsic: Add a CPU pm notifier to restore the IMSIC on exit
  arm64: dts: renesas: r9a09g087: Add ICU support
  arm64: dts: renesas: r9a09g077: Add ICU support
  irqchip: Add RZ/{T2H,N2H} Interrupt Controller (ICU) driver
  ...
This commit is contained in:
Linus Torvalds
2026-02-10 14:01:40 -08:00
parent 66bbe4a8ed 6054b10c32
commit dc855b7771
27 changed files with 1172 additions and 120 deletions
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236
Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml Normal file
View File

@@ -0,0 +1,236 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/renesas,r9a09g077-icu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/{T2H,N2H} Interrupt Controller
maintainers:
- Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
allOf:
- $ref: /schemas/interrupt-controller.yaml#
description:
The Interrupt Controller (ICU) handles software-triggered interrupts
(INTCPU), external interrupts (IRQ and SEI), error interrupts and DMAC
requests.
properties:
compatible:
oneOf:
- const: renesas,r9a09g077-icu # RZ/T2H
- items:
- enum:
- renesas,r9a09g087-icu # RZ/N2H
- const: renesas,r9a09g077-icu
reg:
items:
- description: Non-safety registers (INTCPU0-13, IRQ0-13)
- description: Safety registers (INTCPU14-15, IRQ14-15, SEI)
'#interrupt-cells':
description: The first cell is the SPI number of the interrupt, as per user
manual. The second cell is used to specify the flag.
const: 2
'#address-cells':
const: 0
interrupt-controller: true
interrupts:
items:
- description: Software interrupt 0
- description: Software interrupt 1
- description: Software interrupt 2
- description: Software interrupt 3
- description: Software interrupt 4
- description: Software interrupt 5
- description: Software interrupt 6
- description: Software interrupt 7
- description: Software interrupt 8
- description: Software interrupt 9
- description: Software interrupt 10
- description: Software interrupt 11
- description: Software interrupt 12
- description: Software interrupt 13
- description: Software interrupt 14
- description: Software interrupt 15
- description: External pin interrupt 0
- description: External pin interrupt 1
- description: External pin interrupt 2
- description: External pin interrupt 3
- description: External pin interrupt 4
- description: External pin interrupt 5
- description: External pin interrupt 6
- description: External pin interrupt 7
- description: External pin interrupt 8
- description: External pin interrupt 9
- description: External pin interrupt 10
- description: External pin interrupt 11
- description: External pin interrupt 12
- description: External pin interrupt 13
- description: External pin interrupt 14
- description: External pin interrupt 15
- description: System error interrupt
- description: Cortex-A55 error event 0
- description: Cortex-A55 error event 1
- description: Cortex-R52 CPU 0 error event 0
- description: Cortex-R52 CPU 0 error event 1
- description: Cortex-R52 CPU 1 error event 0
- description: Cortex-R52 CPU 1 error event 1
- description: Peripherals error event 0
- description: Peripherals error event 1
- description: DSMIF error event 0
- description: DSMIF error event 1
- description: ENCIF error event 0
- description: ENCIF error event 1
interrupt-names:
items:
- const: intcpu0
- const: intcpu1
- const: intcpu2
- const: intcpu3
- const: intcpu4
- const: intcpu5
- const: intcpu6
- const: intcpu7
- const: intcpu8
- const: intcpu9
- const: intcpu10
- const: intcpu11
- const: intcpu12
- const: intcpu13
- const: intcpu14
- const: intcpu15
- const: irq0
- const: irq1
- const: irq2
- const: irq3
- const: irq4
- const: irq5
- const: irq6
- const: irq7
- const: irq8
- const: irq9
- const: irq10
- const: irq11
- const: irq12
- const: irq13
- const: irq14
- const: irq15
- const: sei
- const: ca55-err0
- const: ca55-err1
- const: cr520-err0
- const: cr520-err1
- const: cr521-err0
- const: cr521-err1
- const: peri-err0
- const: peri-err1
- const: dsmif-err0
- const: dsmif-err1
- const: encif-err0
- const: encif-err1
clocks:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- reg
- '#interrupt-cells'
- '#address-cells'
- interrupt-controller
- interrupts
- interrupt-names
- clocks
- power-domains
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
icu: interrupt-controller@802a0000 {
compatible = "renesas,r9a09g077-icu";
reg = <0x802a0000 0x10000>,
<0x812a0000 0x50>;
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 4 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 5 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 7 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 8 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 9 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 13 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 14 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 15 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 16 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 17 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 18 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 23 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 408 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 409 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 412 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 413 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 414 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 415 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 416 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 417 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 418 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "intcpu0", "intcpu1", "intcpu2",
"intcpu3", "intcpu4", "intcpu5",
"intcpu6", "intcpu7", "intcpu8",
"intcpu9", "intcpu10", "intcpu11",
"intcpu12", "intcpu13", "intcpu14",
"intcpu15",
"irq0", "irq1", "irq2", "irq3",
"irq4", "irq5", "irq6", "irq7",
"irq8", "irq9", "irq10", "irq11",
"irq12", "irq13", "irq14", "irq15",
"sei",
"ca55-err0", "ca55-err1",
"cr520-err0", "cr520-err1",
"cr521-err0", "cr521-err1",
"peri-err0", "peri-err1",
"dsmif-err0", "dsmif-err1",
"encif-err0", "encif-err1";
clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
power-domains = <&cpg>;
};

1
Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
View File

@@ -22,6 +22,7 @@ properties:
compatible:
enum:
- renesas,r9a09g047-icu # RZ/G3E
- renesas,r9a09g056-icu # RZ/V2N
- renesas,r9a09g057-icu # RZ/V2H(P)
'#interrupt-cells':

4
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
View File

@@ -108,7 +108,9 @@ properties:
riscv,ndev:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Specifies how many external interrupts are supported by this controller.
Specifies how many external (device) interrupts are supported by this
controller. Note that source 0 is reserved in PLIC, so the valid
interrupt sources are 1 to riscv,ndev inclusive.
clocks: true

38
Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
View File

@@ -15,8 +15,7 @@ allOf:
description: |
The Interrupt Router (INTR) module provides a mechanism to mux M
interrupt inputs to N interrupt outputs, where all M inputs are selectable
to be driven per N output. An Interrupt Router can either handle edge
triggered or level triggered interrupts and that is fixed in hardware.
to be driven per N output.
Interrupt Router
+----------------------+
@@ -64,9 +63,14 @@ properties:
interrupt-controller: true
'#interrupt-cells':
const: 1
enum: [1, 2]
description: |
The 1st cell should contain interrupt router input hw number.
Number of cells in interrupt specifier. Depends on ti,intr-trigger-type:
- If ti,intr-trigger-type is present: must be 1
The 1st cell should contain interrupt router input hw number.
- If ti,intr-trigger-type is absent: must be 2
The 1st cell should contain interrupt router input hw number.
The 2nd cell should contain interrupt trigger type (preserved by router).
ti,interrupt-ranges:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
@@ -82,9 +86,22 @@ properties:
- description: |
"limit" specifies the limit for translation
if:
required:
- ti,intr-trigger-type
then:
properties:
'#interrupt-cells':
const: 1
description: Interrupt ID only. Interrupt type is specified globally
else:
properties:
'#interrupt-cells':
const: 2
description: Interrupt ID and corresponding interrupt type
required:
- compatible
- ti,intr-trigger-type
- interrupt-controller
- '#interrupt-cells'
- ti,sci
@@ -105,3 +122,14 @@ examples:
ti,sci-dev-id = <131>;
ti,interrupt-ranges = <0 360 32>;
};
- |
interrupt-controller {
compatible = "ti,sci-intr";
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <2>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <131>;
ti,interrupt-ranges = <0 360 32>;
};