bybrooklyn/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-04-18 14:53:58 -04:00
Code Issues Packages Projects Releases Wiki Activity

dt-bindings: display: lvds-data-mapping: Add 30-bit RGB pixel data mappings

Browse Source 
Add "jeida-30" and "vesa-30" data mappings that are compatible with JEIDA
and VESA respectively.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20241104032806.611890-8-victor.liu@nxp.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Liu Ying
2024-11-04 11:28:00 +08:00
committed by Dmitry Baryshkov
parent 606410292f
commit e316074878
1 changed files with 31 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
Documentation/devicetree/bindings/display/lvds-data-mapping.yaml
View File

@@ -26,12 +26,17 @@ description: |
Device compatible with those specifications have been marketed under the
FPD-Link and FlatLink brands.
This bindings also supports 30-bit data mapping compatible with JEIDA and
VESA.
properties:
data-mapping:
enum:
- jeida-18
- jeida-24
- jeida-30
- vesa-24
- vesa-30
description: |
The color signals mapping order.
@@ -60,6 +65,19 @@ properties:
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
- "jeida-30" - 30-bit data mapping compatible with JEIDA and VESA. Data
are transferred as follows on 5 LVDS lanes.
Slot 0 1 2 3 4 5 6
________________ _________________
Clock \_______________________/
______ ______ ______ ______ ______ ______ ______
DATA0 ><__G4__><__R9__><__R8__><__R7__><__R6__><__R5__><__R4__><
DATA1 ><__B5__><__B4__><__G9__><__G8__><__G7__><__G6__><__G5__><
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B9__><__B8__><__B7__><__B6__><
DATA3 ><_CTL3_><__B3__><__B2__><__G3__><__G2__><__R3__><__R2__><
DATA4 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
- "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
Data are transferred as follows on 4 LVDS lanes.
@@ -72,6 +90,19 @@ properties:
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
- "vesa-30" - 30-bit data mapping compatible with VESA. Data are
transferred as follows on 5 LVDS lanes.
Slot 0 1 2 3 4 5 6
________________ _________________
Clock \_______________________/
______ ______ ______ ______ ______ ______ ______
DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
DATA4 ><_CTL3_><__B9__><__B8__><__G9__><__G8__><__R9__><__R8__><
Control signals are mapped as follows.
CTL0: HSync