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drm/amdgpu: Modify the contiguous flags behaviour
Now we have two flags for contiguous VRAM buffer allocation.
If the application request for AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
it would set the ttm place TTM_PL_FLAG_CONTIGUOUS flag in the
buffer's placement function.
This patch will change the default behaviour of the two flags.
When we set AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
- This means contiguous is not mandatory.
- we will try to allocate the contiguous buffer. Say if the
allocation fails, we fallback to allocate the individual pages.
When we setTTM_PL_FLAG_CONTIGUOUS
- This means contiguous allocation is mandatory.
- we are setting this in amdgpu_bo_pin_restricted() before bo validation
and check this flag in the vram manager file.
- if this is set, we should allocate the buffer pages contiguously.
the allocation fails, we return -ENOSPC.
v2:
- keep the mem_flags and bo->flags check as is(Christian)
- place the TTM_PL_FLAG_CONTIGUOUS flag setting into the
amdgpu_bo_pin_restricted function placement range iteration
loop(Christian)
- rename find_pages with amdgpu_vram_mgr_calculate_pages_per_block
(Christian)
- Keep the kernel BO allocation as is(Christain)
- If BO pin vram allocation failed, we need to return -ENOSPC as
RDMA cannot work with scattered VRAM pages(Philip)
v3(Christian):
- keep contiguous flag handling outside of pages_per_block
calculation
- remove the hacky implementation in contiguous flag error
handling code
v4(Christian):
- use any variable and return value for non-contiguous
fallback
v5: rebase to amd-staging-drm-next branch
Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Suggested-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
committed by
Alex Deucher
parent
f851b078b1
commit
e362b7c8f8
@@ -153,8 +153,10 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
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else
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places[c].flags |= TTM_PL_FLAG_TOPDOWN;
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if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
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if (abo->tbo.type == ttm_bo_type_kernel &&
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flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
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places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
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c++;
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}
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@@ -967,6 +969,10 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
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if (!bo->placements[i].lpfn ||
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(lpfn && lpfn < bo->placements[i].lpfn))
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bo->placements[i].lpfn = lpfn;
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if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS &&
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bo->placements[i].mem_type == TTM_PL_VRAM)
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bo->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS;
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}
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r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
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