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drm/amd/display: dce80, 100, 110 and 112 to dce ipp refactor

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Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin
2017-04-24 16:30:58 -04:00
committed by Alex Deucher
parent 86b6a203b9
commit e6303950ea
15 changed files with 171 additions and 848 deletions
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12
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
View File

@@ -174,7 +174,8 @@ static void dce_ipp_program_input_lut(
struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
/* power on LUT memory */
REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1);
if (REG(DCFE_MEM_PWR_CTRL))
REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1);
/* enable all */
REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7);
@@ -199,7 +200,8 @@ static void dce_ipp_program_input_lut(
}
/* power off LUT memory */
REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0);
if (REG(DCFE_MEM_PWR_CTRL))
REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0);
/* bypass prescale, enable legacy LUT */
REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
@@ -250,3 +252,9 @@ void dce_ipp_construct(
ipp_dce->ipp_shift = ipp_shift;
ipp_dce->ipp_mask = ipp_mask;
}
void dce_ipp_destroy(struct input_pixel_processor **ipp)
{
dm_free(TO_DCE_IPP(*ipp));
*ipp = NULL;
}

24
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h
View File

@@ -23,8 +23,8 @@
*
*/
#ifndef _DCE_DCE_IPP_H_
#define _DCE_DCE_IPP_H_
#ifndef _DCE_IPP_H_
#define _DCE_IPP_H_
#include "ipp.h"
@@ -46,7 +46,6 @@
SRI(PRESCALE_VALUES_GRPH_G, DCP, id), \
SRI(PRESCALE_VALUES_GRPH_B, DCP, id), \
SRI(INPUT_GAMMA_CONTROL, DCP, id), \
SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
SRI(DC_LUT_WRITE_EN_MASK, DCP, id), \
SRI(DC_LUT_RW_MODE, DCP, id), \
SRI(DC_LUT_CONTROL, DCP, id), \
@@ -54,6 +53,14 @@
SRI(DC_LUT_SEQ_COLOR, DCP, id), \
SRI(DEGAMMA_CONTROL, DCP, id)
#define IPP_DCE100_REG_LIST_DCE_BASE(id) \
IPP_COMMON_REG_LIST_DCE_BASE(id), \
SRI(DCFE_MEM_PWR_CTRL, CRTC, id)
#define IPP_DCE110_REG_LIST_DCE_BASE(id) \
IPP_COMMON_REG_LIST_DCE_BASE(id), \
SRI(DCFE_MEM_PWR_CTRL, DCFE, id)
#define IPP_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
@@ -85,7 +92,6 @@
IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \
IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \
IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \
IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh), \
IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \
IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \
IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \
@@ -97,7 +103,11 @@
IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \
IPP_SF(DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh)
#define IPP_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \
#define IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh)
#define IPP_DCE120_MASK_SH_LIST_SOC_BASE(mask_sh) \
IPP_SF(DCP0_CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \
IPP_SF(DCP0_CUR_CONTROL, CURSOR_EN, mask_sh), \
IPP_SF(DCP0_CUR_CONTROL, CURSOR_MODE, mask_sh), \
@@ -223,4 +233,6 @@ void dce_ipp_construct(struct dce_ipp *ipp_dce,
const struct dce_ipp_shift *ipp_shift,
const struct dce_ipp_mask *ipp_mask);
#endif /* _DCE_DCE_IPP_H_ */
void dce_ipp_destroy(struct input_pixel_processor **ipp);
#endif /* _DCE_IPP_H_ */