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drm/amd/display: dce80, 100, 110 and 112 to dce ipp refactor

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Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin
2017-04-24 16:30:58 -04:00
committed by Alex Deucher
parent 86b6a203b9
commit e6303950ea
15 changed files with 171 additions and 848 deletions
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73
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
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@@ -37,7 +37,7 @@
#include "dce/dce_stream_encoder.h"
#include "dce110/dce110_mem_input.h"
#include "dce110/dce110_mem_input_v.h"
#include "dce110/dce110_ipp.h"
#include "dce/dce_ipp.h"
#include "dce/dce_transform.h"
#include "dce/dce_opp.h"
#include "dce/dce_clocks.h"
@@ -168,30 +168,6 @@ static const struct dce110_mem_input_reg_offsets dce100_mi_reg_offsets[] = {
}
};
static const struct dce110_ipp_reg_offsets dce100_ipp_reg_offsets[] = {
{
.dcp_offset = (mmDCP0_CUR_CONTROL - mmCUR_CONTROL),
},
{
.dcp_offset = (mmDCP1_CUR_CONTROL - mmCUR_CONTROL),
},
{
.dcp_offset = (mmDCP2_CUR_CONTROL - mmCUR_CONTROL),
},
{
.dcp_offset = (mmDCP3_CUR_CONTROL - mmCUR_CONTROL),
},
{
.dcp_offset = (mmDCP4_CUR_CONTROL - mmCUR_CONTROL),
},
{
.dcp_offset = (mmDCP5_CUR_CONTROL - mmCUR_CONTROL),
}
};
/* set register offset */
#define SR(reg_name)\
.reg_name = mm ## reg_name
@@ -213,6 +189,28 @@ static const struct dce_disp_clk_mask disp_clk_mask = {
CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
};
#define ipp_regs(id)\
[id] = {\
IPP_DCE100_REG_LIST_DCE_BASE(id)\
}
static const struct dce_ipp_registers ipp_regs[] = {
ipp_regs(0),
ipp_regs(1),
ipp_regs(2),
ipp_regs(3),
ipp_regs(4),
ipp_regs(5)
};
static const struct dce_ipp_shift ipp_shift = {
IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
};
static const struct dce_ipp_mask ipp_mask = {
IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
};
#define transform_regs(id)\
[id] = {\
XFM_COMMON_REG_LIST_DCE100(id)\
@@ -563,22 +561,18 @@ static struct transform *dce100_transform_create(
}
static struct input_pixel_processor *dce100_ipp_create(
struct dc_context *ctx,
uint32_t inst,
const struct dce110_ipp_reg_offsets *offsets)
struct dc_context *ctx, uint32_t inst)
{
struct dce110_ipp *ipp =
dm_alloc(sizeof(struct dce110_ipp));
struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp));
if (!ipp)
if (!ipp) {
BREAK_TO_DEBUGGER();
return NULL;
}
if (dce110_ipp_construct(ipp, ctx, inst, offsets))
return &ipp->base;
BREAK_TO_DEBUGGER();
dm_free(ipp);
return NULL;
dce_ipp_construct(ipp, ctx, inst,
&ipp_regs[inst], &ipp_shift, &ipp_mask);
return &ipp->base;
}
static const struct encoder_feature_support link_enc_feature = {
@@ -674,7 +668,7 @@ static void destruct(struct dce110_resource_pool *pool)
dce100_transform_destroy(&pool->base.transforms[i]);
if (pool->base.ipps[i] != NULL)
dce110_ipp_destroy(&pool->base.ipps[i]);
dce_ipp_destroy(&pool->base.ipps[i]);
if (pool->base.mis[i] != NULL) {
dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i]));
@@ -1005,8 +999,7 @@ static bool construct(
goto res_create_fail;
}
pool->base.ipps[i] = dce100_ipp_create(ctx, i,
&dce100_ipp_reg_offsets[i]);
pool->base.ipps[i] = dce100_ipp_create(ctx, i);
if (pool->base.ipps[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(